cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
5,445 Views
Registered: ‎06-14-2016

MAP errors using BUFPLL

Hi to everyone,

 

I'm trying to build two IOSerDes interfaces in a single Spartan6 (XC6SLX25) in order to communicate with other 2 FPGA. The iserdes part works fine but due to the clock needed by the oserdes the MAP give me this errors:

 

ERROR:Place - ConstraintResolved NO placeable site for
   IOSerDes_Inst/tx_bufpll_dataout
ERROR:Place - ConstraintResolved NO placeable site for
   IOSerDes_Inst/tx_bufpll_clkout
ERROR:Place:1238 - Component
   "Inst_Clk_Generators_Oserdes_Eth/pll_oserdes/pll_base_inst/PLL_ADV" does not
   have a feasible site.
   There are 6 potential locations for the component:
ERROR:Place:1201 - Component
   <Inst_Clk_Generators_Oserdes_Eth/pll_oserdes/pll_base_inst/PLL_ADV> of type
   PLL is not placeable because it has locked loads placed in regions:
   CLOCKREGION_X0Y0 CLOCKREGION_X0Y0.
   There is a restriction that the clock loads of a PLL must be in a
   horizontally adjacent clock region to the PLL. It is recommended that a BUFG
   be used for this clock signal so that the clock loads can be placed anywhere
   on the device. If the clock driver or clock loads are locked or area grouped,
   please ensure that they are constrained to horizontally adjacent clock
   regions.
ERROR:Place:1201 - Component
   <Inst_Clk_Generators_Oserdes_Eth/pll_oserdes/pll_base_inst/PLL_ADV> of type
   PLL is not placeable because it has locked loads placed in regions:
   CLOCKREGION_X0Y0 CLOCKREGION_X0Y0.
   There is a restriction that the clock loads of a PLL must be in a
   horizontally adjacent clock region to the PLL. It is recommended that a BUFG
   be used for this clock signal so that the clock loads can be placed anywhere
   on the device. If the clock driver or clock loads are locked or area grouped,
   please ensure that they are constrained to horizontally adjacent clock
   regions.
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

In my design I've a PLL for the generation of the GCLK and IOCLK clocks and two BUFPLL in order to generate also the SerDesStrobe in SDR interface. The outputs of the BUFPLLs drive in parallel the 2 IOSerDes_Block in the images which contain the OSERDES primitive for the data and clock_SDR generation.

 

SCHEM2.png

 

SCHEM3.png

 

I've also tried to remove the LOC constraint in the ucf file but this led to an unroutable signal during the PAR:

 

Release 14.7 - par P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

Fri Jun 24 16:40:24 2016

1 signals are not completely routed.

WARNING:ParHelpers:360 - Design is not completely routed.

   IOSerDes_Inst/txserdesstrobe
   
   

All the I/O related to my IOSERDES application must be locked in the bank2. Here there is part of my ucf file:

 

net "slave_daisy_chain" IOSTANDARD = LVCMOS33;
net "slave_daisy_chain" loc = P7;
net "present_signal_sx" IOSTANDARD = LVCMOS33;
net "present_signal_dx" IOSTANDARD = LVCMOS33;
net "present_signal_sx" loc = T9;
net "present_signal_dx" loc = P6;

# Input Chain BUS (CONNECTION AS SX BOARD).
net "right_board_present" 	loc = R9;
net "right_board_present" 	IOSTANDARD = LVCMOS33;
net "SXBOARD_serial_data_in_p" 		IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;		
net "SXBOARD_serial_data_in_n"		IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;		
net "SXBOARD_ext_data_clk_p" 		IOSTANDARD = LVDS_33 	 | DIFF_TERM = TRUE;			
net "SXBOARD_ext_data_clk_n"			IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;		
net "SXBOARD_send_dataclk_p"			IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;		
net "SXBOARD_send_dataclk_n" 		IOSTANDARD = LVDS_33  	| DIFF_TERM = TRUE;			
net "SXBOARD_serial_data_out_p" 	IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;			
net "SXBOARD_serial_data_out_n" 	IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;			
net "block_is_ready" 				IOSTANDARD = LVCMOS33;
net "led" 						IOSTANDARD = LVCMOS33;
net "SXBOARD_serial_data_in_p" 		loc = L10	;	
net "SXBOARD_serial_data_in_n"		loc = M10	;	
net "SXBOARD_ext_data_clk_p" 		loc = M9	;		
net "SXBOARD_ext_data_clk_n"			loc = N8	;	
net "SXBOARD_send_dataclk_p"			loc = P8	;	
net "SXBOARD_send_dataclk_n" 		loc = T8	;		
net "SXBOARD_serial_data_out_p" 	loc = N9	;		
net "SXBOARD_serial_data_out_n" 	loc = P9	;		
net "block_is_ready" 		loc = D1 ;
net "led" 						loc = A7;

NET "SXBOARD_ext_data_clk_p" TNM_NET = "SXBOARD_ext_data_clk_p";
TIMESPEC TS_SXBOARD_ext_data_clk_p = PERIOD "SXBOARD_ext_data_clk_p" 8 ns HIGH 50 %;


# Input Chain BUS (CONNECTION AS RX BOARD).
net "left_board_present" 						IOSTANDARD = LVCMOS33;
net "left_board_present" 				loc = T6;

net "DXBOARD_serial_data_in_p" 	IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;		
net "DXBOARD_serial_data_in_n"	IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;		
net "DXBOARD_ext_data_clk_p" 	IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;			
net "DXBOARD_ext_data_clk_n"		IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;		
net "DXBOARD_send_dataclk_p"		IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;		
net "DXBOARD_send_dataclk_n" 	IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;			
net "DXBOARD_serial_data_out_p" IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;			
net "DXBOARD_serial_data_out_n" IOSTANDARD = LVDS_33  | DIFF_TERM = TRUE;			

net "DXBOARD_serial_data_in_p" 	loc = N5	;	
net "DXBOARD_serial_data_in_n"	loc = P5	;	
net "DXBOARD_ext_data_clk_p" 		loc = R7	;		
net "DXBOARD_ext_data_clk_n"		loc = T7	;
	
net "DXBOARD_send_dataclk_p"		loc = R5	;	
net "DXBOARD_send_dataclk_n" 		loc = T5	;		
net "DXBOARD_serial_data_out_p" 	loc = P4	;		
net "DXBOARD_serial_data_out_n" 	loc = T4	;
		
NET "DXBOARD_ext_data_clk_p" TNM_NET = "DXBOARD_ext_data_clk_p";
TIMESPEC TS_DXBOARD_ext_data_clk_p = PERIOD "DXBOARD_ext_data_clk_p" 8 ns HIGH 50 %;

 

I'm sure the problem is related to a bad managment of the clock resources of the Spartan but i'm not able to figure it out. Thanks in advance for your help.

0 Kudos
1 Reply
Highlighted
Visitor
Visitor
5,385 Views
Registered: ‎06-14-2016

Re: MAP errors using BUFPLL

EDIT: I'm trying different design. I've also removed all the loc constraint but i added the " LOC = BANK2 " constraint in order to have all my I/O pins in that bank.

 

I've tried this architectures:

 

  • 2 BUFPLL for each IOSerdDes_Block in order to generate data and a SDR clock. 1 BUFIO2 for each IOSerdDes_Block for the deserialization.  TOT 4 BUFPLL, 2 BUFIO
  • 1 BUFPLL for each IOSerdDes_Block  in order to generate data and a DDR clock. 2 BUFIO2 for each IOSerdDes_Block for the deserialization. TOT 2 BUFPLL, 4 BUFIO
  • 2 BUFPLL for all  the IOSerdDes_Block in order to generate data and a SDR clock. 1 BUFIO2 for each IOSerdDes_Block for the deserialization.  TOT 2 shared BUFPLL, 2 BUFIO
  • 1 BUFPLL for all  the IOSerdDes_Block in order to generate data and a DDR clock. 2 BUFIO2 for each IOSerdDes_Block for the deserialization.  TOT 1 shared BUFPLL, 4 BUFIO

In all this architectures i get MAP errors related to the location of the clock resources. Any suggestions? 

0 Kudos