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sha@hys
Explorer
Explorer
8,352 Views
Registered: ‎05-31-2015

MAP stage optimising BRAM

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Hello,

 

                         I am using two BRAMs in my VHDL xilinx ISE project. The AXI BRAMblocks are a part of microblaze and microblaze is instantiated in VHDL program. One of the BRAM is used only by microblaze side and other is used as shared memory between VHDL and microblaze, so one of the the ports of this memory is taken out as external ports to VHDL side and is forced from there. At the MAP stage the shared BRAM is fully optimised away marking it as unused block and other memory stays. I tried register equivalent removal attribute to NO but still the problem exists. I dont understand when I write to block from VHDL side how can that be said as unused block.

 

                        Kindly suggest a method to avoid this optimisation.

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arpansur
Moderator
Moderator
15,967 Views
Registered: ‎07-01-2015

Hi sha@hys,

 

Can you please try putting save attribute on the connecting signals?

Please go through page 245 and 246 of following link:

http://china.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

 

Thanks,
Arpan

Thanks,
Arpan
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arpansur
Moderator
Moderator
15,968 Views
Registered: ‎07-01-2015

Hi sha@hys,

 

Can you please try putting save attribute on the connecting signals?

Please go through page 245 and 246 of following link:

http://china.xilinx.com/support/documentation/sw_manuals/xilinx14_7/cgd.pdf

 

Thanks,
Arpan

Thanks,
Arpan
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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View solution in original post

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