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Visitor
Visitor
10,359 Views
Registered: ‎08-16-2011

MIG_36_1 UCF ERROR

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After all, good morning.

 

I am a Electronic Developer in a Mexican company named Hydra Technologies. I am working with a MIG Module for a DDR32M16 Memory and we are now using the IDE v13.1 from Xilinx. I use the Core Generator to customize the MIG Module, but when I want to generate the Program File, I get a lot of errors in the UCF file generated by the Core Generator.

We are now using the next device:

-Spartan3E | XC3S1200E | FG320 | Speed -4 


Here I set you some of the errors that I got:

 

ERROR:ConstraintSystem:59 - Constraint <NET
   "Module/infrastructure_top0/clk_dcm0/clk" TNM_NET = "clk0";> [C:/Hydra Technologies/FPGA Projects/DDR Control v0.1.0/MIG_PIN_13_1.ucf(35)]: NET
   "Module/infrastructure_top0/clk_dcm0/clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET
   "Module/infrastructure_top0/clk_dcm0/clk90" TNM_NET = "clk90";> [C:/Hydra Technologies/FPGA Projects/DDR Control v0.1.0/MIG_PIN_13_1.ucf(39)]: NET
   "Module/infrastructure_top0/clk_dcm0/clk90" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:58 - Constraint <NET
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" TNM_NET = "fifo_we_clk";> [C:/Miguel Marina/FPGA Projects/DDR Control
   v0.1.0/MIG_PIN_13_1.ucf(42)]: NET
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/cl
   k" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <NET
   "Module/top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/clk" TNM_NET = "fifo_waddr_clk";> [C:/Hydra Technologies/FPGA Projects/DDR
   Control v0.1.0/MIG_PIN_13_1.ucf(45)]: NET
   "Module/top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_ins
   t/clk" does not match any design objects.
ERROR:ConstraintSystem:59 - Constraint <INST
   "Module/infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;>
   [C:/Hydra Technologies/FPGA Projects/DDR Control v0.1.0/MIG_PIN_13_1.ucf(294)]:
   INST "Module/infrastructure_top0/cal_top0/cal_ctl0" not found.  Please verify
   that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "Module/infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;>
   [C:/Hydra Technologies/FPGA Projects/DDR Control v0.1.0/MIG_PIN_13_1.ucf(295)]:
   INST "Module/infrastructure_top0/cal_top0/tap_dly0" not found.  Please verify
   that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:58 - Constraint <NET
   "Module/top_00/data_path0/data_read0/fifo*_wr_en*"                  
   MAXDELAY = 3200 ps;> [C:/Hydra Technologies/FPGA Projects/DDR Control
   v0.1.0/MIG_PIN_13_1.ucf(395)]: NET
   "Module/top_00/data_path0/data_read0/fifo*_wr_en*" does not match any design
   objects.
ERROR:ConstraintSystem:58 - Constraint <NET
   "Module/top_00/data_path0/data_read0/fifo*_wr_addr[*]"           MAXDELAY =
   6800 ps;> [C:/Hydra Technologies/FPGA Projects/DDR Control
   v0.1.0/MIG_PIN_13_1.ucf(401)]: NET
   "Module/top_00/data_path0/data_read0/fifo*_wr_addr[*]" does not match any
   design objects.
ERROR:ConstraintSystem:59 - Constraint <INST
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC = SLICE_X3Y29;> [C:/Hydra Technologies/FPGA Projects/DDR Control
   v0.1.0/MIG_PIN_13_1.ucf(481)]: INST
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_ins
   t" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC = SLICE_X1Y29;> [C:/Hydra Technologies/FPGA Projects/DDR Control
   v0.1.0/MIG_PIN_13_1.ucf(482)]: INST
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_ins
   t" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst" LOC = SLICE_X3Y57;> [C:/Hydra Technologies/FPGA Projects/DDR Control
   v0.1.0/MIG_PIN_13_1.ucf(588)]: INST
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_ins
   t" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst" LOC = SLICE_X1Y57;> [C:/Hydra Technologies/FPGA Projects/DDR Control
   v0.1.0/MIG_PIN_13_1.ucf(589)]: INST
   "Module/top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_ins
   t" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

 

 

Module is the name of the MIG in the TOP LEVEL of my project. I route the IO with the correct address for the MIG and for Top Module IO.

 

I Attached to you the UCF file. Thank you for your time.

 

Mechatronic Engineer Miguel Angel Marina Garduño

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Visitor
Visitor
13,709 Views
Registered: ‎08-16-2011

I resolve the problem. I tried to generate the bit file on Windows XP and it fail, but in Windows 7 I generate the bit file with any problem. I think that can be an error of the IDE.

 

Regards!!!

 

Mechatronic Engineer Miguel Angel Marina Garduño

Hydra Technologies

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Highlighted
Visitor
Visitor
10,353 Views
Registered: ‎08-16-2011

This error take place even when I work with the MIG Module without using my TopLevel!!!!!

 

I need help, If you know about a MIG from another IDE vertion that is stable, please mention it, I can use it if it is necesary.

 

Does anybody implement the MIG module?

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Xilinx Employee
Xilinx Employee
10,341 Views
Registered: ‎10-23-2007

Are you using the same options for implementation as listed in the ise_flow.bat or .sh output from MIG (in the par directory)?

 

Is it possible your top level doesn't match exactly?  You could try using '*' instead of 'Module' below.

 

If you run the ise_flow.bat script directly in the example_design/par from MIG without changing anything at all, does it implement properly?

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

The ERROR messages mean that that indicated name is not present in your final netlist.  I would suggest that you remove the UCF file for the flow, place and route the design and open it in FPGA Editor.  This will allow you to look at the final hierarchical names that were used in your design to determine why the mismatch is present.

 

I noticed that your project is in a directory that contains spaces.  There are known issues with the ISE tools in dealing with spaces and it is strongly recommended that you eliminate the spaces from your working areas.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor
Visitor
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Registered: ‎08-16-2011

Thank you. I change the path of my files, and y delete the top level that I use. I try to get the program generation with the MIG module without using my code, and I get the same errors, the errors do not take place in all the lines, only in some lines, especially in lines that use the " * " symbol and in clock lines.

 

This is the errors using only the MIG Module generated by Xilinx Tools:

 

ERROR:ConstraintSystem:59 - Constraint <NET "infrastructure_top0/clk_dcm0/clk"
   TNM_NET = "clk0";>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(36)]: NET
   "infrastructure_top0/clk_dcm0/clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "infrastructure_top0/clk_dcm0/clk90"
   TNM_NET = "clk90";>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(40)]: NET
   "infrastructure_top0/clk_dcm0/clk90" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:58 - Constraint <NET
   "top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk"
   TNM_NET = "fifo_we_clk";>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(44)]: NET
   "top_00/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" does
   not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <NET
   "top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/clk"
   TNM_NET = "fifo_waddr_clk";>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(47)]: NET
   "top_00/data_path0/data_read_controller0/gen_wr_addr*fifo*_wr_addr_inst/clk"
   does not match any design objects.
ERROR:ConstraintSystem:59 - Constraint <INST
   "infrastructure_top0/cal_top0/cal_ctl0" AREA_GROUP = cal_ctl;>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(296)]: INST
   "infrastructure_top0/cal_top0/cal_ctl0" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "infrastructure_top0/cal_top0/tap_dly0" AREA_GROUP = cal_ctl;>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(297)]: INST
   "infrastructure_top0/cal_top0/tap_dly0" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:58 - Constraint <NET
   "top_00/data_path0/data_read0/fifo*_wr_en*"                    MAXDELAY =
   3200 ps;> [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(394)]:
   NET "top_00/data_path0/data_read0/fifo*_wr_en*" does not match any design
   objects.
ERROR:ConstraintSystem:58 - Constraint <NET
   "top_00/data_path0/data_read0/fifo*_wr_addr[*]"           MAXDELAY = 6800
   ps;> [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(400)]: NET
   "top_00/data_path0/data_read0/fifo*_wr_addr[*]" does not match any design
   objects.
ERROR:ConstraintSystem:59 - Constraint <INST
   "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" LOC
   = SLICE_X3Y29;>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(480)]: INST
   "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" LOC
   = SLICE_X1Y29;>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(481)]: INST
   "top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst" LOC
   = SLICE_X3Y57;>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(587)]: INST
   "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
   "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst" LOC
   = SLICE_X1Y57;>
   [C:/MiguelMarina/FPGA_Projects/DDR_CONTROL_v0.02/MIG_PIN.ucf(588)]: INST
   "top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst" not
   found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

 

I attach you the UCF generated without modifications.

Thank you for your time!!!!

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Instructor
Instructor
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Registered: ‎07-21-2009

Is this a timing-constraints-only problem, or a more general 'can't find the bits and pieces' type problem?

 

I wonder if ISE is including the MIG-generated source code files in your design.

 

Here's a test:  one by one, use PROJECT > ADD SOURCE to add the various MIG source code files to your project.  See if your results change.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Visitor
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Registered: ‎08-16-2011

I add the files again, but it do not result, I got the same errors.

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Visitor
Visitor
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Registered: ‎08-16-2011

Thank you, I run the *.bat file and it implements correctly the code. Did I have to configure the IDE to compile with the same options like in the "bat" script? And how can I get help to know what options of my IDE I have to change?.

 

Tank you very much!!!

 

___________________________________________________________________

Mechatronic Engineer Miguel Angel Marina Garduño

Research and Development in Hydra Technologies

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Visitor
Visitor
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Registered: ‎08-16-2011

I resolve the problem. I tried to generate the bit file on Windows XP and it fail, but in Windows 7 I generate the bit file with any problem. I think that can be an error of the IDE.

 

Regards!!!

 

Mechatronic Engineer Miguel Angel Marina Garduño

Hydra Technologies

View solution in original post

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Highlighted
10,237 Views
Registered: ‎11-07-2011

Hallo progman64, hallo jspaldings,

 

I do have the same problems, using ISE 13.2 (WebPack). (Iam a student working on my Bachelor-Thesis)

 

I include all .vhd - files from the user_design/rtl and the .ucf - file from user_design/par.

When I try to implement the MIG design (without any other top components, so mig_36_1.vhd is the top module) the same errors appear.

 

Can one of you guys please explain exactly what I need to do after running the ise_flow.bat? Or do I need to execute the ise_flow.bat in a special way?

The only change I recognize is the new(and empty) ise_flow_results.txt - file in the par folder.

 

Thank you in advance
Jan

 

ps: I dont have any space in the datapath, I am using win7.

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Visitor
Visitor
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Registered: ‎10-18-2007

I am having the same problem.  MIG 3.6.1   ISE 14.1.

 

I am trying to get the example design (unmodified) to generate a bit file.

 

I've used PlanAhead to verify that the nets exist and are spelled correctly.

 

I've looked at the source code for the generated UCF file and the Verilog design files and the cited nets are there.

 

Perhaps it's the way I've started the project.  I did as follows:

 

1) started a new project with no source files.

2) ran MIG to generate the design.

3) used "Add Source" to add the source files found in the par and rtl subdirectories

4) run the compile.

 

Synthesize works, but Translate always fails.

 

Here is the text of the first of the errors:

 

ERROR:ConstraintSystem:59 - Constraint <NET
   "/DDR2_SDRAM/infrastructure_top0/clk_dcm0/clk" TNM_NET = "clk0";>
   [ipcore_dir/DDR2_SDRAM/example_design/par/DDR2_SDRAM.ucf(42)]: NET
   "/DDR2_SDRAM/infrastructure_top0/clk_dcm0/clk" not found.  Please verify
   that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <NET "infrastructure_top0/clk_dcm0/clk90"
   TNM_NET = "clk90";>
   [ipcore_dir/DDR2_SDRAM/example_design/par/DDR2_SDRAM.ucf(46)]: NET
   "infrastructure_top0/clk_dcm0/clk90" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:58 - Constraint <NET
   "main_00/top0/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk" TNM_NET = "fifo_we_clk";>
   [ipcore_dir/DDR2_SDRAM/example_design/par/DDR2_SDRAM.ucf(51)]: NET
   "main_00/top0/data_path0/data_read_controller0/gen_wr_en*fifo*_wr_en_inst/clk
   " does not match any design objects.

 

Someone in another thread suggested to use PlanAhead to see if the nets are there, which is why I did that and that seems OK.  His other suggestion was to use "brute" force and use the wild card *.  This didn't work until I substituted */*/clk0 for infrastructure_top0/clk_dcm0/clk.  The same is true for the second of the errors.  However, other errors generated did not stop with wild cards.  I don't like the idea of wild cards used like this anyway, something that is generated like this ought to simply work.

 

Can anyone please help?

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Instructor
Instructor
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Registered: ‎07-21-2009

S,

 

This thread has already been marked as 'solved'.  Please start a new thread for your problem.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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