UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
5,406 Views
Registered: ‎03-08-2009

MIG, FIFOs, DDR Sdram sustained transfer rate, sizing and speed questions

Can somebody give me a "gut feeling" of what sustained transfer rate I can create using the following high level data flow:

and if what I'd like to do is doable?

 

16bit ADC ->  Spartan ->  DDR SDRAM

 

The ADC needs to run at some speed <= 100mhz, faster would be nice.

 

The DDR SDRAM would be a 16bit wide, 133MHZ chip or two.

 

Digging a little deeper into design, there are 2 modes of operation.

 

a) upload mode - can be very slow, and is not an issue, the design is simple and straight forward:

 

   cypress FX2 -> spartan -> SDRAM.

 

b) In *SIMPLE* "collect-mode" where 100mhz sample rate to the SDRAM is critical

 

   100mhz ADC -> spartan -> SDRAM

 

c) I would *REALLY* like to be able to do this instead:

 

16bitADC ->  (event-detect) -> FIFO ->  (run length compression)  -> FIFO ->  SDRAM CONTROLLER ->  DDR SDRAM

 

Where the SPARTAN does the following:

    (d) the event detect

    (e) if needed, an incomming FIFO

    (f) the run-length compression

    (g) if needed, a FIFO in front of the DDR controller

    (h) the  DDR controller.

 

The "event detect" is quite simple, monitoring the input and output values of the FIFO looking for a large step change

 

The "rle compression" is simplistic - it would store 2 values to the SDRAM,

 

(i) a rough "ADC VALUE" and

(j) The "repeat count" for that rough ADC value.

 

 

When the event begins, the RLE engine does this:

 

Store 0xFFFF/0xFFFF (saturated ADC value and count) to the SDRAM.

 

Then, the RLE engine would operate in 'pass through' mode.

 

Eventually, the event ends, and 0xFFFF/0xFFFF is stored again, and the RLE engine turns back on.

 

My assumption is this:

    

   (1) the adc rate is 100mhz

   (2) the sdram rate is 133mhz

   

  Thus, I have about 30% extra clocks in the fpga to get the job done.

   Thus, it should be reasonably 'do-able' 

 

==============

 

 

What I don't know, and I'm looking for guidence for is this:

 


I have no means to judge if my idea is even viable, or "sure that's do-able" but requires a $1000 fpga chip.

 

 

k)   Can somebody tell me "ball park numbers" what the sustained rate through the generated Xlinx FIFOs in a spartan chip.

 

l)  How deep can I reasonably make these FIFOs?

   ie:  512 entries? 1024 entries? or even more then that.

   I have no idea.

 

m)   Which Spartan should I be looking at? (please suggest a part number)

 

important factors:

 

n) At this stage: Having to re-layout a board because I need a bigger/different spartan is deadly.

   Switching later (for cost savings reasons) is not an issue.

 

o) the design really needs to be usable/extendable by what is in the free web pack.

 

p)  BGA packages need to be avoided.

 

q) Given the above recommend chip - what 'utilization percentage' might I end up with?

 

      I'd like enough room left in the chip to create some reasonable CPU periphal.

      Low end: a simple CPU periphial UART, with some configuration registers.

      High end:  A simple Ethernet interface.

 

     I don't want to be at 89% and begging for room.

 

r)  Same goes with "chip frequency" - yes I know that as things get more complex, the actual rate slows way down.

 

s) If this last set of requirements 'is a bit too much'  What do you think is a reasonable goal?

 

  I have no means to judge what I should be looking at.

 

Thanks.

 

0 Kudos
2 Replies
Historian
Historian
5,370 Views
Registered: ‎02-25-2008

Re: MIG, FIFOs, DDR Sdram sustained transfer rate, sizing and speed questions

You ask a lot.

 

A reasonable approach might be to actually code up the design. Simulate it and be sure that it's functionally correct.

 

Then start trying to implement the design using the tools. Target the largest chip in the family you choose. The tools will tell you the design's resource usage. You can then change the target to an appropriate-sized device.

 

Sure, this means that the FPGA design and the PCB layout are not done in parallel, but it ensures that you don't make a "deadly" mistake.

 

Nobody can give you a proper usage estimate  because we don't know the particulars of the design. Something that might appear simple and straightforward might turn out to be pretty complicated and blow your estimate out of the water.

 

-a

----------------------------Yes, I do this for a living.
0 Kudos
Explorer
Explorer
5,338 Views
Registered: ‎09-11-2007

Re: MIG, FIFOs, DDR Sdram sustained transfer rate, sizing and speed questions

I only skimmed your post, as it was long.  You asked,

"Can somebody give me a "gut feeling" of what sustained transfer rate I can create using the following high level data flow:

and if what I'd like to do is doable? "

 

Here's a data point.  With 266MHz DDR2 SDRAM and a Virtex5 MIG controller, doing only writes with linear incrementing address, I get over 90% of the maximum memory bandwidth.

 

HTH,

Barry

0 Kudos