01-08-2010 02:03 PM
I am currenty busy with the MIG DDR SDRAM controller. I use Spartan 3A DSP fgf676 -4 speedgrade 3400k gate. I generate a DDR-SDRAM (Micron 32Mx16 -75 grade DDR model)with MIG 2.3V with ISE 10.1.03. Then I use create_ise.bat in example design to create ISE project and then I do the post route simulaiton of the design (setup time mode). Everything is left as default in design and I see the violations in the simulation because of the fifo_wr_en as
top/uut/main_00_top0_data_path0_data_read_controller0_gen_wr_en_0_fifo_0_wr_en_inst_delay_ff/ : Warning: /X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK;
Expected := 7.236 ns; Observed := 4.746 ns; At : 14833.918 ns
and this violation causes error signal to rise to high as expected.
I understand the error but why the generated design does not work? Where am I wrong? Can you suggest something?
01-08-2010 09:28 PM
Are you using xilinx board ? ( I mean to ask if you have same UCF as given in example project or you have your own ucf file )
01-09-2010 03:44 AM
I am not using xilinx board. Actually we are designing our board and I am trying to determine pin location for fpga. However, design that is generated by MIg give violation in post route simulation. Moreover, I am not give any constraint to MIG only controller is implemented in FPGA. For data and system control bank-3, address and system clock bank-0. All the availiable for MIG.
Can any one face such a question? Help...
01-09-2010 12:12 PM
Here I would suggest you to first select the banks and when UCF file is generated add your pin locations to UCF file .. MIG generates the placement constrain in ucf file. Thus when you select the bank and then write pin locations in UCF with placement constrains already present in UCF file there is less chance of timing violation.
01-09-2010 12:23 PM
01-10-2010 04:23 PM
can you please provide your exact part no for DDR ? I tried to create DDR controller for --MT46V32M16XX-75. I hope this is the same part number you have used. I synthesized the project and analyzed timing report and it is not giving any timing violatoins. Have you tried to pass it through xilinx timing analyzer ?
01-11-2010 04:41 AM
Yeah in implementation and sytnhesis there is no problem. Can you simulate your generated design in post route simulation for example design and monitor the error signal? Then please give mne the result.