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Visitor sozyurek
Visitor
8,133 Views
Registered: ‎05-21-2009

MIG Spartan 3A DSP Post Route Violation

Hi everyone,

 

I am currenty busy with the MIG DDR SDRAM controller. I use Spartan 3A DSP fgf676 -4 speedgrade 3400k gate. I generate a DDR-SDRAM (Micron 32Mx16 -75 grade DDR model)with MIG 2.3V with ISE 10.1.03. Then I use create_ise.bat in example design to create ISE project and then I do the post route simulaiton of the design (setup time mode). Everything is left as default in design and I see the violations in the simulation because of the fifo_wr_en as

 

top/uut/main_00_top0_data_path0_data_read_controller0_gen_wr_en_0_fifo_0_wr_en_inst_delay_ff/ : Warning: /X_FF SETUP  Low VIOLATION ON I WITH RESPECT TO CLK;
  Expected := 7.236 ns; Observed := 4.746 ns; At : 14833.918 ns

 

and this violation causes error signal to rise to high as expected.

 

I understand the error but why the generated design does not work?  Where am I wrong? Can you suggest something?

 

 

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6 Replies
Observer patkionkar
Observer
8,120 Views
Registered: ‎03-02-2009

Re: MIG Spartan 3A DSP Post Route Violation

hi,

 

Are you using xilinx board ? ( I mean to ask if you have same UCF as given in example project or you have your own ucf file )

 

Regards,

Onkar Patki 

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Visitor sozyurek
Visitor
8,109 Views
Registered: ‎05-21-2009

Re: MIG Spartan 3A DSP Post Route Violation

Hi Onkar,

 

I am not using xilinx board. Actually we are designing our board and I am trying to determine pin location for fpga. However, design that is generated by MIg give violation in post route simulation. Moreover, I am not give any constraint to MIG only controller is implemented in FPGA. For data and system control bank-3, address and system clock bank-0. All the availiable for MIG.

 

Can any one face such a question? Help...

 

Regards,

Serkan.

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Observer patkionkar
Observer
8,090 Views
Registered: ‎03-02-2009

Re: MIG Spartan 3A DSP Post Route Violation

Hi ,

 

Here I would suggest you to first select the banks and when UCF  file is generated add your pin locations to UCF file .. MIG generates the placement constrain in ucf file. Thus when you select the bank and then write pin locations in UCF with placement constrains already present in UCF file there is less chance of timing violation.

 

Regards,

Onkar Patki 

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Visitor sozyurek
Visitor
8,088 Views
Registered: ‎05-21-2009

Re: MIG Spartan 3A DSP Post Route Violation

Yeah I know but I have problem with project generated with MIg. As you know MIG generate test project in user design and example design folders as output. In example design I run create_ise.bat this batch file create a project and set the necessary ise options. Then I run post route simulation and I see the violations. But thanks for your comment. Could you try create MIG project for ISE spartan-3A DSP?
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Observer patkionkar
Observer
8,062 Views
Registered: ‎03-02-2009

Re: MIG Spartan 3A DSP Post Route Violation

Hi ,

 

can you please provide your exact part no for DDR ? I tried to create  DDR controller for --MT46V32M16XX-75. I hope this is the same part number you have used. I synthesized the project and analyzed timing report and it is not giving any timing violatoins. Have you tried to pass it through xilinx timing analyzer ?

 

 

Regards,

Onkar Patki

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Visitor sozyurek
Visitor
8,050 Views
Registered: ‎05-21-2009

Re: MIG Spartan 3A DSP Post Route Violation

Hi Onkar,

 

Yeah in implementation and sytnhesis there is no problem. Can you simulate your generated design in post route simulation for example design and monitor the error signal? Then please give mne the result.

 

Best Regard,

 

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