04-04-2013 10:10 AM
While reviewing an existing design, a violation of the standard rule using 2 FF's to sync an asynchronous signal was discovered. In this case, the logic is looking for an edge detect, but only uses a single FF to capture the first edge of the signal.
Is there a way to estimate what the settling time of the metastable condition would be from the first FF, through the AND gate, to the input of second FF? The clock rate is slow (<10MHz), so there is more than 100ns allowed for settling.
04-04-2013 11:28 AM
You'd need the exact timing numbers to know what the routing delays are, but it would be
unusual for the total to exceed a handful of nanoseconds. If you can find the path in a
timing report, the slack would be the number that says how much settling time you have.
If not, you could find the routes in the FPGA editor and get the delay, then add the datasheet
values for clock to out of the driving flop, combinatorial delays through the logic for the AND
gate (this could be a LUT or other logic, you'd need to inspect the slice in the FPGA editor)
and then subtract the total from the clock period. Even if you waved your hands, and said
it couldn't be more than 20 ns and you have 80 ns to settle, I would expect that any
metastable event that takes that long to settle would be a once in the age of the universe
sort of event.
09-21-2015 04:55 AM
Hello! I am doing a Survey paper about metastability in the Spartan-6 board. If i understand it correct there are a lot of timing issues to considerate that can create an asynchronous signal in a D flip-flop. This can lead to a metastable state in worst case scenario. For that topic i have some information.
The problem arise is when i try to find what kind of D flip-flop is used in Spartan 6 and on what kind of bulk it is placed in , i.e. 65nm CMOS bulk. I need this for creating some evaluation of the characteristics of the flop.