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Explorer
Explorer
5,159 Views
Registered: ‎06-15-2010

Migration of DPRAM

Hello,

I'd like to ask community for help on the folloving topic. I have pretty old project, which I try to move on the newer tools. This project is targeted on Spartan-3. It uses IP Cores to create block-RAM based dualport memories. Those cores are very old, in xco file I see the string

SELECT Dual_Port_Block_Memory Spartan3 Xilinx,_Inc. 5.0

My device is xc3s1500, which has 32 block memories and 30 or so multipliers. I use 25 multipliers and 30 block RAMs.

If I use 11.5 tools to compile the project and regenerate cores as is, then its fine. Then I created IP Cores of the last version manually and replaced old ones. But that time I got error. It says that block RAMs and multipliers share some resources, so its impossible to use my amount of multipliers and block RAMs simutaneously.

 

So, it looks like previous versions of dualport memory IP core did not use those shared resources and can coexist with multipliers. Is it possible to loosen some restriction or parameter of IP core to resemble old core behaviour?

 

Thanks in advance.

 

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Teacher
Teacher
5,158 Views
Registered: ‎09-09-2010

Re: Migration of DPRAM

Why can't you just keep using the old version(s) of tools?

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"If it don't work in simulation, it won't work on the board."
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Explorer
Explorer
5,156 Views
Registered: ‎06-15-2010

Re: Migration of DPRAM

Well, I did not expected recommendation to keep 6.1 tools.

We planning to move that design to Spartan-6. Already we faced a trouble with block RAMs use, which was not detected in tools prior to 12.1, I mean requirement of certain port width configuration. Just to be sure we planning upgrade to the recent tools. Meanwhile to make sure porting process is OK we update tools with former chip.

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Teacher
Teacher
5,152 Views
Registered: ‎09-09-2010

Re: Migration of DPRAM

I would suggest that if 11.5 works for both the old and new chips, use that until you have migrated the design, then consider updating further.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Historian
Historian
5,143 Views
Registered: ‎02-25-2008

Re: Migration of DPRAM


@rrlagic wrote:

Well, I did not expected recommendation to keep 6.1 tools.

We planning to move that design to Spartan-6. Already we faced a trouble with block RAMs use, which was not detected in tools prior to 12.1, I mean requirement of certain port width configuration. Just to be sure we planning upgrade to the recent tools. Meanwhile to make sure porting process is OK we update tools with former chip.


If you're updating, you'd do well to also rewrite your code to infer the BRAMs rather than instantiating them, or worse, using the Core Generator.

----------------------------Yes, I do this for a living.
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Explorer
Explorer
5,131 Views
Registered: ‎06-15-2010

Re: Migration of DPRAM


@bassman59 wrote:

If you're updating, you'd do well to also rewrite your code to infer the BRAMs rather than instantiating them, or worse, using the Core Generator.


 Yes, I don't mind minor updates to the code. For example, I found, that IP cores for binary counters (yes, they were there) already obsolete. As synthesis tools improve, its better to code them in HDL rather then rely on IP cores. So I modified that part without hesitation.

 

As to memories, I feel some lack of knowledge. I was taugth to use IP Cores and specify, whether I want to use block memory or distributed. So I tried to customize IP core of the production version. And did not succeed - I cannot have like 30 BRAMs and 25 MULTs in the same design because, although cores of previous, but hidden and usupported versions could coexist. I wonder, if I can force them to coexist.

 

But from your comment I feel my skill is obsolete too. Could you please elaborate a little bit more? Do you mean that using IP Cores to make dualport RAM is wrong habit? Should I try to code it in HDL?

 

Thanks in advance

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Historian
Historian
5,123 Views
Registered: ‎02-25-2008

Re: Migration of DPRAM


@rrlagic wrote:
But from your comment I feel my skill is obsolete too. Could you please elaborate a little bit more? Do you mean that using IP Cores to make dualport RAM is wrong habit? Should I try to code it in HDL

It's a lot easier to maintain your own code than it is to worry that the vendor- (or 3rd-party) supplied code will change from release to release.

----------------------------Yes, I do this for a living.
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