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Visitor
Visitor
3,991 Views
Registered: ‎03-09-2010

Minimum JTAG clock (TCK)

Hi,

    I am using spartan 6 FPGA in my design. I want to configure the  FPGA through processor. So i have connected the processor GPIOs to FPGA JTAG signals (TMS, TDI, TDO & TCK).

 

Mainly I want to know what will be the minimum  JTAG clock (TCK) that the Spartan 6 FPGA can accept?

 

Regards,

Rahul.

 

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Adventurer
Adventurer
3,979 Views
Registered: ‎08-13-2007

0Hz Should be the minimum the datasheet doesn't actually specify the minimum. Max is specification is 33MHz

 

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Visitor
Visitor
3,213 Views
Registered: ‎04-15-2011

Hi Rahul

I am facing some difficulty in JTAG chain congiguration through freescale P1012 processor.

Can you send me the procedure for JTAG cofig.

I need to write XSVF through this.

 

regards

Vijay

 

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