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Visitor dabell-cc
Visitor
5,607 Views
Registered: ‎01-18-2013

Multi-Source Signals, what are my options?

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Hi all,

I'm looking for some clarification on an XST warning my code generates. 

 

"WARNING:Xst:2040 - Unit playground: 3 multi-source signals are replaced by logic (pull-up yes): SCLK_MLTSRCEDGE, SDA_MLTSRCEDGE, SEN_MLTSRCEDGE"

 

I'm targeting a Spartan-3E XC3S1200E-4FG400. I'm in ISE 10.1.03.

 

Some background. I'm trying to read/write to another chip using it's 3-line serial comms. I've made 'Read' and 'Write' components, and I'm instantiating them in my top-level module. Each Read/Write module has an 'enable' input and a 'done' output of type STD_LOGIC. The desired effect here was that I could chain components together and they would fire off one after the other. They are all driven by a single clock component. 

 

I've had a read work already, and I'm trying to test out writing.

The current test configuration is:

  U1: clock  -- sent to everything

   |

   |-U2: reset  -- the other chip needs to be in a functioning state 

   |   |     

   |-U3: read  -- read from the other chip's registers

   |   |

   |-U4: write  -- write to that register

   |   |

   |-U5: read  -- read that register to see that the write worked.

 

After each component I'm careful to set the 3 comms lines (SDA, SCLK, SEN) to 'Z' -- they are of type STD_LOGIC as well. I've put each component through simulation during writing, and put the whole system through simulation which appears to work wonderfully.

 

So my issue, I think, is that:

1) I expect to be able to drive an output with multiple tri-stateable sources (after all, isn't that what they're for?) as long as only one of them is active at any given time (the others are 'Z').

2) The synthesis is pulling the lines up. These lines are active high, so the other chip is expecting constant communication and that's not what is happening. Pulling them low might work out, provided they still transition high when necessary.

 

Could anyone tell me how to effectively use tristateable outputs to drive a single signal?

Perhaps how to set the logic to pull the lines down, not up?

Alternately, discuss the correct way of going about what I'm trying to do?

 

Thanks in advance!

 

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Historian
Historian
7,249 Views
Registered: ‎02-25-2008

Re: Multi-Source Signals, what are my options?

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Are you trying to use tristate logic inside the FPGA?

 

Because you can't do that.

 

Tristates only at the FPGA pins. Xilinx stopped putting tristate-able longlines in FPGAs after the XC4000-series devices from the late '90s. Basically such structures are slow and you can do a much better job with multiplexors when you're in the chip.

 

----------------------------Yes, I do this for a living.
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6 Replies
Historian
Historian
7,250 Views
Registered: ‎02-25-2008

Re: Multi-Source Signals, what are my options?

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Are you trying to use tristate logic inside the FPGA?

 

Because you can't do that.

 

Tristates only at the FPGA pins. Xilinx stopped putting tristate-able longlines in FPGAs after the XC4000-series devices from the late '90s. Basically such structures are slow and you can do a much better job with multiplexors when you're in the chip.

 

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
5,594 Views
Registered: ‎08-13-2007

Re: Multi-Source Signals, what are my options?

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You may also find this useful - although you are attempting to infer them not instantiate them.

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/What-is-BUFT-in-this-RTL/m-p/111838

 

As was said - you can't do this. Only the actual top-level output can be tristated.

 

bt

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Visitor dabell-cc
Visitor
5,587 Views
Registered: ‎01-18-2013

Re: Multi-Source Signals, what are my options?

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@bassman59 wrote:

Are you trying to use tristate logic inside the FPGA?

 

Because you can't do that.

 

Tristates only at the FPGA pins. Xilinx stopped putting tristate-able longlines in FPGAs after the XC4000-series devices from the late '90s. Basically such structures are slow and you can do a much better job with multiplexors when you're in the chip.

 


I think that clears it up a bit, thank you. I failed to understand that tristates could only exist at the pin, not internally.

 

I had considered multiplexing, but when adding significantly more reads/writes this will likely get large and messy, sounds like a redesign in my thinking is required. Suggestions to that effect are welcome, I don't have much experience with system design in VHDL (that's got to change), only a small module here and there.

 

For this test, I will certainly multiplex my three outputs.

Thanks for the clarification, and a speedy response! (Especially on a Friday).

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Visitor dabell-cc
Visitor
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Registered: ‎01-18-2013

Re: Multi-Source Signals, what are my options?

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@barriet wrote:

You may also find this useful - although you are attempting to infer them not instantiate them.

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/What-is-BUFT-in-this-RTL/m-p/111838

 

As was said - you can't do this. Only the actual top-level output can be tristated.

 

bt


 

I did search for the answer before posting and came across that thread, unfortunately that didn't cause it to click with me.

Reading it again with the mindset of "tristate at the pins, not internally" did make more sense, I originally didn't see that subtlety.

 

Is the effect of converting tristate to logic supposed to yield a faster circuit? Also, why did it make the decision to pull-up and can I specify a preference for pull-down? Frowned upon or not, I like to know what's possible. 

 

Either way it sounds like this is something to avoid in the future, I'll work on that. 

Thanks for your response, it was useful for me to re-read that thread with my new knowledge.

 

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Xilinx Employee
Xilinx Employee
5,577 Views
Registered: ‎08-13-2007

Re: Multi-Source Signals, what are my options?

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The internal tristates were removed from silicon. So synthesis really only has two options from an implementation perspective:

-give you an error and force you to rewrite it

-try to remap it to logic (e.g. muxes) and issue a warning so you know this

 

When I said "you can't do that" I meant with respect to getting what you actually specified. I'll admit I've never tried to let synthesis (e.g. XST here) do this and then look at the results closely to see what it actually does in these situations. I've always rewritten my RTL here on these newer devices so better control the technology mapping rather than rely on some behind-the-scenes transformation.

 

bt

 

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Visitor dabell-cc
Visitor
5,555 Views
Registered: ‎01-18-2013

Re: Multi-Source Signals, what are my options?

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@barriet wrote:

 I've always rewritten my RTL here on these newer devices so better control the technology mapping rather than rely on some behind-the-scenes transformation.

 

bt

 


Best to not leave things unknown, it's true. 

Thanks again.

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