02-12-2013 09:58 AM
I am new to the FPGA world. I am trying to build a code using Spartan 6 device. My requirement is to be able to switch my ios from 3.3V to 1.5V as and when required(manually). Is there a way in FPGA to do this? I dont want to burn an image on the device every time I do this. My intention is to have a control bit that I can change to let the FPGA know the voltage domain....
02-12-2013 10:11 AM
The Vccio voltage may be changed externally (a programmable power supply).
Inside tyhe FPGA, the IOB drive level will now be from the new supply. If you select a LVCMOS 3.3v 12 mA IO standard, at a lower voltage, the minimum current drive will no longer be 12 mA, but it will still be functioning, at perhaps half that value (6 mA) or so.
No change to the bitstream is required: just an underwstanding that the output will be weaker at a lower voltage that it would be at a higher voltage (or, the reverse: stronger at a higher voltage than at a lower voltage).
02-13-2013 08:39 AM
There will also be slower timing at lower Vcco voltage due to the reduced drive strength. One
problem is that the tools won't know that you have switched Vcco to 1.5V and so the clock
to output numbers in the timing report will not show you the actual worst case under these
conditions. IBIS models also don't cover cases of incorrect Vcco usage. So basically you
may need to do some experimentation to see how this affects the output drive / timing and
then decide if your system can live with it.
02-18-2013 05:30 AM
I am planning to have one of my IO banks running at 1.5V and the other at 3.3V and duplicate the pins. I will internally select the one I need and tristate the other so it does not affect the outputs. My worry now is about the input pins. Because my input is coming on both pins and if the singal on the incoming line is 3.3V, I am afraid if this is going to damage the 1.5V pins...If yes, is there a way I can avoid this. I have several input pins and cant have so many jumpers on my board...
02-18-2013 06:33 AM
Actually whether or not the pin is an input, you would have 3.3V signals on the 1.5V bank, but
this is O.K. on Spartan 6, because it does not have clamp diodes to Vcco except when using PCI
IO standards. You just need to be very careful not to enable the drive on both banks at once. Be
sure that the startup state of the drive enables is off.
02-18-2013 06:54 AM
This is exactly what I am worried about. It will be the same track that will have the 3.3V signal sometimes and other times it will have 1.5V signal. I want to implement a scheme in fpga to take care of this. Do you know if I can disable the inputs when the 1.5V inputs. I control the input signal voltage level so I will always know the level of the incoming signal. I just want to be able to disable the 1.5V input pin when its not used.
02-18-2013 07:13 AM
You don't need to disable input pins. They can handle 3.3V indefinitely (see the "absolute maximum specifications"). The input thresholds will be based on Vcco for LVCMOS, but exceeding Vcco is not a problem as long as you don't exceed the maximum tolerable input voltage. If you look at Table 9 in DS162 you will see a range for Vih on all LVCMOS standards that has a maximum input voltage of 4.1V regardless of Vcco. Note that this is not the case for most earlier FPGA families including Spartan 3 and 3E.
So basically you can do what you want and should not need jumpers as long as you can guarantee that you're not driving both sets of outputs at the same time.