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Visitor beequantel
Visitor
3,331 Views
Registered: ‎05-18-2015

No output on OSERDES2

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Hello,

 

I'm trying to use a OSERDES2 to serialize datas. The simulation of my complete design works fine but I've no output signal when my FPGA is programmed (I already checked that my measure was ok generating a square signal on the same pad).

 

After further readings I think I respect the clocking methodology of the SERDES. I use a SelectIO Interface Wizard which instantiate automatically a BUFPLL. This BUFPLL is feeded by 2 clocks generated with a PLL_BASE.

 

During design implementation I get a warning : clock net clk_950 with clock driver pll_i/clkout2_buf drives no clock pins.

This could be the source of my problem but this signal (from PLL_BASE) is correctly connected to the BUFPLL. The simulation of my complete design wouldn't be working if it were not the case.

 

 

serders_out : out_serdes8
PORT MAP (
	-- From the device out to the system
	DATA_OUT_FROM_DEVICE    => diode_trig_8_reg,
	DATA_OUT_TO_PINS        => synchro_out_vector,

	-- Clock and reset signals
	CLK_IN                  => clk_high,
	CLK_DIV_IN              => clk_low,
	LOCKED_IN               => pll_locked,
	--LOCKED_OUT              : out   std_logic;
	IO_RESET                => '0'
);

 

I can provide the design project in attachments if needed (it's a very simple design).

 

Best regards,

 

bee

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Visitor beequantel
Visitor
5,856 Views
Registered: ‎05-18-2015

Re: No output on OSERDES2

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I reduced the frequency at 570 MHz to give it a try and it's working fine.

So I increased the frequency at 855 MHz, still working. So I got back to 950 MHz => Working.... I did not change anything else that the clocking wizard... I've no more timing warnings... 

 

Comparing the project I attached to this message and the one I got now I find that the clocking wizard removed the BUFG when I changed the frequencies. So that was my problem, there was no need for a BUFG instantiation from the PLL.

 

I don't think the limit is 750 mpbs, I've another design working at 1 GHz on Spartan-6 (Speed grade 3).

Here my Spartan 6 is speed grade 2 so the PLL is limited at 950 MHz.

 

thanks for the help

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5 Replies
Explorer
Explorer
3,325 Views
Registered: ‎04-05-2016

Re: No output on OSERDES2

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Take a look at the HDL Libraries Guide for Spartan-6, page 205.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_hdl.pdf

 

Have you instantiated the primitive correct?

 

Is it possible that you're holding something in reset with the incorrect polarity?

 

Does your simulation simulate the top-module of your design, or a sub-entity?

 

What are the clock rates you are using?  Have you defined them in your ucf file? ( this is likely not the issue, but possible you've got a clock on a non-clock net and the tools aren't picking that up ).

 

What version of the ISE tools are you using?

 

Can you export the schematic of the post-synth design to a pdf/image and post it?

 

It sounds like something is getting optimized out ( that simulation doesn't do ).  If you post the full project I'll see if I can take a look.

 

 

 

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Visitor beequantel
Visitor
3,314 Views
Registered: ‎05-18-2015

Re: No output on OSERDES2

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Thanks for your quick reply, answers in text.


@timduffy wrote:

Take a look at the HDL Libraries Guide for Spartan-6, page 205.

 

https://www.xilinx.com/support/documentation/sw_manuals/xilinx11/spartan6_hdl.pdf

 

Have you instantiated the primitive correct?

 

I hope so, the primitives are automatically instantiated by the wizards.

 

Is it possible that you're holding something in reset with the incorrect polarity?

 

I don't think so the simulation would not be working.

 

Does your simulation simulate the top-module of your design, or a sub-entity?

 

I simulate the top module and sub-entity, both working fine

 

What are the clock rates you are using?  Have you defined them in your ucf file? ( this is likely not the issue, but possible you've got a clock on a non-clock net and the tools aren't picking that up ).

 

I defined the input clock of my device in ucf file, the constraints on PLL_BASE generated clock are automatically inferred during synthesis. This input clock is at 95MHz. I generate 950MHz and 128MHz (950/8) by the PLL.

 

What version of the ISE tools are you using?

 

The last one : 14.7

 

Can you export the schematic of the post-synth design to a pdf/image and post it?

 

I would be easier to take a look at the design.

 

It sounds like something is getting optimized out ( that simulation doesn't do ).  If you post the full project I'll see if I can take a look.

 

I joined it to this message.

 

 


 

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Explorer
Explorer
3,300 Views
Registered: ‎04-05-2016

Re: No output on OSERDES2

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Hmm, so 950mhz likely is too high for the oseries2.  Look at page 93 of UG381:

 

https://www.xilinx.com/support/documentation/user_guides/ug381.pdf

 

You're trying to run the interface at 950mb/s ( 1 bit @ 950mhz ), where the upper limit of the Spartan-6 is 750mbps ( in 3:1 mode ).

 

This warning is displayed during implementation:

 

 

WARNING:Pack:2768 - At least one timing constraint is impossible to meet because component switching limit violations have been detected for
   a constrained component. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the
   Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to evaluate the component switching limit violations in
   more detail. Evaluate the datasheet for alternative configurations for the component that could allow the frequencies requested in the
   constraint. Otherwise, the timing constraint covering this component might need to be modified to satisfy the component switching limits
   specified in the datasheet.

 

Is it possible for you to run slower than 950mhz?

 

-TD

 

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Visitor beequantel
Visitor
5,857 Views
Registered: ‎05-18-2015

Re: No output on OSERDES2

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I reduced the frequency at 570 MHz to give it a try and it's working fine.

So I increased the frequency at 855 MHz, still working. So I got back to 950 MHz => Working.... I did not change anything else that the clocking wizard... I've no more timing warnings... 

 

Comparing the project I attached to this message and the one I got now I find that the clocking wizard removed the BUFG when I changed the frequencies. So that was my problem, there was no need for a BUFG instantiation from the PLL.

 

I don't think the limit is 750 mpbs, I've another design working at 1 GHz on Spartan-6 (Speed grade 3).

Here my Spartan 6 is speed grade 2 so the PLL is limited at 950 MHz.

 

thanks for the help

View solution in original post

Explorer
Explorer
3,212 Views
Registered: ‎04-05-2016

Re: No output on OSERDES2

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Hmm. Well I'm glad I could be the catalyst for your success!