02-07-2016 08:27 PM
I am new to SPI DAC so am posting for geting a solution to my problem. I am implementing a 4-PAM generation using FPGA. The flow is as follows. I already generated 4-PAM using a parallel DAC in my hardware however I am also trying to prototype my design in FPGA. THe design is as follows. First using series of flipflops and xor gates I generated PRBS data. The unit clock delayed data and the original data is to go to DAC. Now here we have a 2 bit DAC which can be easily implemented in a parallel DAC however to convert this to serial is one problem. 2nd is how do I configure the DAC to its working state. Please help me get the result of DAC.
I am posting the waveforms expected out of DAC and the inputs going to DAC.
02-08-2016 05:23 AM
I don't know if you are using a Spartan-3E Starter Kit but even if you are not you might find this reference design and its documentation of some use...
PicoBlaze Processor D/A Converter Controller
Demonstrates the Linear Technology LTC2624 digital-to-analog (D/A) converter. The SPI-based communication to the D/A controller is performed using the PicoBlaze processor controller.
02-08-2016 08:00 AM
It looks like the LTC2624 is about 2 orders of magnitude slower than you need to generate the waveforms you posted. If it's OK to run the prototype much slower than the actual hardware you could use it. Have you found the datasheet on the Linear Tech website? Commands to the DAC's SPI interface, including commands to set the voltage, require 24 bits at a maximum clock rate of 50 MHz, so at best you could update the voltage every 480 ns using continuous writes. That assumes you only need to use one output of the DAC. If you need more, then your write rate per output would be slowed by a factor of 1/N where N is the number of outputs you need to update.
02-15-2016 06:21 AM
There are some serial-input DACs that can run faster by reducing the word size. However the LTC2624 does not appear to have this feature, so the fact that you only need 2 bits doesn't help. Anyway its settling time is way too long to run at the data rates you're trying to do. You are probably best off building a 2-bit DAC with resistors and two outputs of the FPGA running LVCMOS with the highest available drive to ensure rail-to-rail outputs.