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14,568 Views
Registered: ‎09-12-2007

OFFSET Constraint with DCM

Hello,
 
I am designing a system which runs on a Spartan 3 at 100MHz.  A microcontroller supplies both the 100MHz clock as well as data on a bus, which changes on the falling edge.  I want to build my system which clocks in data on the rising edge of the clock.  I have decided to use a DCM with GCLK being driven by the CLK0 output on the DCM, and feedback going from GCLK back to the feedback pin to eliminate clock skew over GCLK buffer.
 
So in the UCF file, I first have the contraint for my clock period:
 
NET "SYSCLK" TNM_NET = "SYSCLK";
TIMESPEC "TS_SYSCLK" = PERIOD "SYSCLK" 105 MHz HIGH 50 %;
 
Next I have the constraint for my NETS
NET "DATABUS<0>"  LOC = "p142" | IOSTANDARD = LVCMOS33 ;
NET "DATABUS<1>"  LOC = "p2" | IOSTANDARD = LVCMOS33 ;
NET "DATABUS<2>"  LOC = "p3" | IOSTANDARD = LVCMOS33 ;
NET "DATABUS<3>"  LOC = "p4" | IOSTANDARD = LVCMOS33 ;
NET "DATABUS<4>"  LOC = "P5" | IOSTANDARD = LVCMOS33 ;
NET "DATABUS<5>"  LOC = "P7" | IOSTANDARD = LVCMOS33 ;
NET "DATABUS<6>"  LOC = "P8" | IOSTANDARD = LVCMOS33 ;
NET "DATABUS<7>"  LOC = "p10" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<0>"  LOC = "P131" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<10>"  LOC = "p124" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<11>"  LOC = "p125" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<12>"  LOC = "p126" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<13>"  LOC = "p128" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<14>"  LOC = "p129" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<15>"  LOC = "p130" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<1>"  LOC = "p132" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<2>"  LOC = "p134" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<3>"  LOC = "p135" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<4>"  LOC = "p136" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<5>"  LOC = "p139" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<6>"  LOC = "p140" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<7>"  LOC = "p141" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<8>"  LOC = "P122" | IOSTANDARD = LVCMOS33 ;
NET "ADDRESSBUS<9>"  LOC = "P123" | IOSTANDARD = LVCMOS33 ;
NET "NWE"  LOC = "p120" | IOSTANDARD = LVCMOS33 ;
NET "NOE"  LOC = "p119" | IOSTANDARD = LVCMOS33 ;
 
Then I define instances of the memory buses under TNM="microcontroller":
 
INST "ADDRESSBUS[*]" TNM = "Microcontroller";
INST "DATABUS[*]" TNM = "Microcontroller";
INST "NWE" TNM = "Microcontroller";
INST "NOE" TNM = "Microcontroller";
 
And lastly, my thought was I should define the setup time for the databus to about 4ns because the data arives at the falling edge (5ns before the rising edge of the clock), and so it should be stable within a nanosecond of the falling edge.

TIMEGRP "Microcontroller" OFFSET = IN 4 ns BEFORE "SYSCLK";

When I run this, the simulation fails:

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing  
                                            |         |    Slack   | Achievable | Errors |    Score  
------------------------------------------------------------------------------------------------------
* TIMEGRP "Microcontroller" OFFSET = IN 4 n | SETUP   |    -6.947ns|    10.947ns|     107|      445043
  s BEFORE COMP "SYSCLK"                    |         |            |            |        |           
------------------------------------------------------------------------------------------------------
  TS_U_DCMModule_CLK0_BUF = PERIOD TIMEGRP  | SETUP   |     2.080ns|     7.443ns|       0|           0
  "U_DCMModule_CLK0_BUF" TS_SYSCLK HIGH     | HOLD    |     1.036ns|            |       0|           0
       50%                                  |         |            |            |        |           
------------------------------------------------------------------------------------------------------
  TS_SYSCLK = PERIOD TIMEGRP "SYSCLK" 105 M | N/A     |         N/A|         N/A|     N/A|         N/A
  Hz HIGH 50%                               |         |            |            |        |           
------------------------------------------------------------------------------------------------------

1 constraint not met.

Here is what I don't understand.  How can the best case SETUP time by 10.947 ns when my period is 10ns.  How can the setup time be LONGER than the period of my clock pulse.
 
Can someone please explain this to me.  Is it delay through the DLL or something.
 
If I remove the TIMEGRP and INST commands from the constraint, it meets timing requirements no problem.
 
Thanks,
Ben
 
 
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6 Replies
Highlighted
14,560 Views
Registered: ‎09-12-2007

Re: OFFSET Constraint with DCM

Just to clarify on my previous post, I wrote "when I run this the simulation fails". I should have written "when I run this the place and route fails". Sorry.
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Visitor
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14,556 Views
Registered: ‎09-12-2007

Re: OFFSET Constraint with DCM

My first concern is that you will implement with this falling/rising edge stuff a 200Mhz interface on common Spartan3 LVCOMS33 IOs. This could be very tight. Try to run on the same edges.

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14,524 Views
Registered: ‎09-12-2007

Re: OFFSET Constraint with DCM

Ok, so how should I go about doing this.
 
The microcontroller outputs 3.3V CMOS signal.  The clock the microcontroller outputs is at 100MHz whether I like it or not.  The memory bus actually changes quite slowly (it doesn't change every clock cycle), but its state always changes on a falling edge of the clock.  I just want to make sure that when my FPGA reads it in, it is stable.
 
So you suggested using a single clock edge.  How do I do this.  Obviously, once the data is within my FPGA, everything runs on one edge.  This is obvious.  How do I deal with the external bus?  My idea was to clock data in on the rising edge, so that I knew it was stable (because it only changes on the falling edge).  As you pointed out though, then I have very small setup times (~4ns).  If I clock my FPGA of the falling edge (the same as the microcontroller), how to I garantee that the FPGA will clock the data in BEFORE the microcontroller changes it?
 
This is just a simple Si Labs C8051F120, 8051 based, microcontroller.  There doesn't seem to be any real specs in terms of hold up and setup times for the external memory interface (EMIF) bus.
 
It seems wasteful to design this as asynchronous, because then I waste two clock cycles doing through two flip-flops.  This adds up to a full 20ns before I even through the CS and let the SRAM do its thing (which takes another 55ns).
 
In any case, the design tool, as I speced before, is telling be best case that it needs a setup time of more than 1 clock cycle.  How is this even possible?  If I hold the signal for 11ns before an edge, doesn't that mean that I didn't meet the hold requirements of the edge previously (where the data had only been on there for 1ns)?
 
Any help anyone could give me would be appreciated A LOT!  This is my first large FPGA project, so I am kinda figuring it out as I go!
 
Ben
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Registered: ‎09-12-2007

Re: OFFSET Constraint with DCM

In case it wasn't obvious from above, the FPGA is being used to do address decoding.  I basically am just using it to read in the Address, and if it is within the SRAM range, to turn on a CS for a 55ns SRAM.  It also has a few internal things (like a quadrature counter) which I also want to map to the memory bus.  The microcontroller is the master of the bus (it always drives the address bus).  The databus may be driven by the microcontroller (on a write), or by either the FPGA or the SRAM on a read, depending on the address.
 
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Visitor
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Registered: ‎09-12-2007

Re: OFFSET Constraint with DCM

You're absolutely right, if dealing with the single clock edges you need to ensure that the clock edge transition comes before the data changes. This is depending on you micro controller, but you can also use the DCMs of the FPGA to align (or eventually phase shifting) the clock to the data.

Concerning the functionality you're planing to integrate into the FPGA this would may also fits into a CPLD, and with a combinatorial only address decoding you may also achieve your design goals (just thinking about an alternative).
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Registered: ‎09-12-2007

Re: OFFSET Constraint with DCM

Thanks,
Your comments really helped.  I see you were totally correct.
 
I used an FPGA because I have some of my FPGA registers within the FPGA also mapped to the memory space.  (If it isn't an address for one of my internal registers, then I enable the SRAM CS).  Each of the those registers is attached to another sub-system in my FPGA which wouldn't fit in a CPLD.
 
I have done what you suggested.  I have build my address decoder totally combinationally.  I made two signals (SRAM_CS and INTERNAL_CS).  If it is for my internal signal, I throw the INTERNAL_CS signal.
 
The thing I missed was that I know when nWE and nOE go low, that the addressbus and databus should be stable, so all I have to do is synchronize the nWE and nOE signals (through a double flip flop) and then once the synchronized output goes low (active), I can clock in the addressbus and databus!  This way I have like 40ns of holdup on the ADDRESSBUS and DATABUS, instead of just 4ns,w hich is what I had when I insisted on reading the addressbus every clock cycle.
 
I respond a little slower this way, but it doesnt matter because the SRAM is 55ns RAM anyways, so my nOE and nWE pulses are several clock cycles anyways to meet the worst case (SRAM) timing.
 
Thanks again for all your help.  I am new to this whole FPGA stuff, so the help was really appreciated.
 
Ben 
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