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Registered: ‎11-10-2009

Output port with default value ('Z') showing wrong electrical level

Hello all,


in the top level of my design I have described a port in the following way:


port : OUT std_logic := 'Z';


The logic which will drive this port in the future is not yet existent so I could think that the FPGA would show a high impedance output at that pin. Unfortunately I can see that the FPGA drives that pin to a clear '0'.


I have an external pull-up resistor in the line driven by that pin, which shows a correct '1' when the FPGA is not programmed.


First I thought that this could be due to the fact that my -g UnusedPin option is "Pull down" and, lacking any logic behind the pin more than the default 'Z' value, the ISE could consider that pin as unused IOB. I set this option to "float" but no difference could be appreciated.


It will also work if I define the port as:


port : OUT std_logic := '1';


which, by the way, is not legal for my hardware.


Can anybody give me a clue about this strange phenomen?

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