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Explorer
Explorer
715 Views
Registered: ‎03-08-2018

PLL Clock generation fail.

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Dear All,

 

I'm trying to make pll clock by using clocking wizard for making HDMI@1080p and HDMI@720p clock as the below,

Input clock is 150Mhz.

Target clock is 10x and 5x clock. then 1500Mhz and 750Mhz.

 

But clock Wizard does not support 1500Mhz.

So What am I supposed to do to get 1500Mhz?

 

 

 

q106.JPG

 

 

 

q107.JPG

 

 

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1 Solution

Accepted Solutions
808 Views
Registered: ‎06-21-2017

Re: PLL Clock generation fail.

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ds162 states that Foutmax  for the PLL is 400MHz when driving a BUFGMUX and 1080MHz when driving a BUFPLL.  These numbers are for the -3 speed grade, others are a bit lower.  You would use a global clock buffer (BUFGMUX) when driving logic inside the FPGA.  The BUFPLL is related to high speed serial IO.

3 Replies
Highlighted
697 Views
Registered: ‎06-21-2017

Re: PLL Clock generation fail.

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What in a Spartan 6 do you expect to run at 750MHz or 1500MHz? 

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Explorer
Explorer
678 Views
Registered: ‎03-08-2018

Re: PLL Clock generation fail.

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@bruce_karaffa I think there are some module of PLL clock generator.

Did I something miss?

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809 Views
Registered: ‎06-21-2017

Re: PLL Clock generation fail.

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ds162 states that Foutmax  for the PLL is 400MHz when driving a BUFGMUX and 1080MHz when driving a BUFPLL.  These numbers are for the -3 speed grade, others are a bit lower.  You would use a global clock buffer (BUFGMUX) when driving logic inside the FPGA.  The BUFPLL is related to high speed serial IO.