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Adventurer
Adventurer
13,437 Views
Registered: ‎08-23-2011

PLL IP core for Spartan6 low power FPGAs

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Hi all,

I m trying to generate PLL core for Spartan 6 FPGAs. I m using Xilinx 13.2 version. In the Xilinx Core generator i can generate PLL core only for VIrtex-5 family FPGAs. Can anyone please tell me how to generate it for Spartan 6?

Thanks in advance.

Regards,

Kiran

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Xilinx Employee
Xilinx Employee
17,629 Views
Registered: ‎11-28-2007

Re: PLL IP core for Spartan6 low power FPGAs

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I would suggest you open a web case with the technical support and ask what current status is. Often times it's pending characterization when moving a core from pre-production to production status.

 


@kchalla wrote:

Hi,

Can anyone please tell me when can be used the clocking wizard 3.2 to generate PLL in Spartan 6 Low Power FPGAs ?? For reference please refer to the above messages.

Is this due to Hardware restrictions or IP core problem?

Thanks in advance,

Best Regards,

Kiran




Cheers,
Jim

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Xilinx Employee
Xilinx Employee
13,431 Views
Registered: ‎11-28-2007

Re: PLL IP core for Spartan6 low power FPGAs

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For Spartan6, Virtex6 and 7 series, you use the "Clocking Wizard" (see the snapshot below) to generate code with clocking primitives such as PLL, DCM. On the first page of the Clocking Wizard window, you can set "Clock Manager Type to "Manual Selection" and then select the primtive you want.

 

ScreenHunter_12.jpg

 


@kchalla wrote:

Hi all,

I m trying to generate PLL core for Spartan 6 FPGAs. I m using Xilinx 13.2 version. In the Xilinx Core generator i can generate PLL core only for VIrtex-5 family FPGAs. Can anyone please tell me how to generate it for Spartan 6?

Thanks in advance.

Regards,

Kiran




Cheers,
Jim
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Adventurer
Adventurer
13,424 Views
Registered: ‎08-23-2011

Re: PLL IP core for Spartan6 low power FPGAs

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Hi Jim,

Thanks for your reply. As it was written in the Clocking Wizard -> Information -> Identifier:

Identifier:

 

xilinx.com:ip:clk_wiz:3.2. You are using Clocking Wizard 3.2 which is a Pre-Production core. Use of this core in production systems is not recommended.

So the above sentence means i can use only for test purpose but not in my project which will go further into production ?

can you please tell me when can i use this core fully functional??

 

I found also something strange in the clock outputs numbering in the ip core. In the second page of ip core generation clock ouputs are numbered clk_out1 to clk_out6 but in the last page they are numbered clk_out0 to clk_out5. I came to know this only when i got an error when i m trying to generate the core.

I selected only one clk_out1 in the second page, when i entered the last page it say that clk_out0 is not configured properly. But i got only one time like that. I tried once again then no problem....

But i would like to inform you regarding the clock output numbers.

 

Regards,

Kiran

 

 

 

 

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Xilinx Employee
Xilinx Employee
13,403 Views
Registered: ‎11-28-2007

Re: PLL IP core for Spartan6 low power FPGAs

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Which device are you using for your CoreGen project? When I look at a Spartan6 project, it shows that the clocking wizard is in production status (see the snapshot below):

 

ScreenHunter_18.jpg

 


@kchalla wrote:

Hi Jim,

Thanks for your reply. As it was written in the Clocking Wizard -> Information -> Identifier:

Identifier:

 

xilinx.com:ip:clk_wiz:3.2. You are using Clocking Wizard 3.2 which is a Pre-Production core. Use of this core in production systems is not recommended.

So the above sentence means i can use only for test purpose but not in my project which will go further into production ?

can you please tell me when can i use this core fully functional??

 

I found also something strange in the clock outputs numbering in the ip core. In the second page of ip core generation clock ouputs are numbered clk_out1 to clk_out6 but in the last page they are numbered clk_out0 to clk_out5. I came to know this only when i got an error when i m trying to generate the core.

I selected only one clk_out1 in the second page, when i entered the last page it say that clk_out0 is not configured properly. But i got only one time like that. I tried once again then no problem....

But i would like to inform you regarding the clock output numbers.

 

Regards,

Kiran

 

 

 

 




Cheers,
Jim
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Adventurer
Adventurer
13,398 Views
Registered: ‎08-23-2011

Re: PLL IP core for Spartan6 low power FPGAs

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Hi Jim,

I m using Spartan 6 Low Power part, xc6slx25l-1ftg256.

I have tried with the part that you have choosen. It is fine with that as you mentioned in your last email. But with the part i have choosen its different.

Regards,

Kiran

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Adventurer
Adventurer
13,359 Views
Registered: ‎08-23-2011

Re: PLL IP core for Spartan6 low power FPGAs

Jump to solution

Hi,

Can anyone please tell me when can be used the clocking wizard 3.2 to generate PLL in Spartan 6 Low Power FPGAs ?? For reference please refer to the above messages.

Is this due to Hardware restrictions or IP core problem?

Thanks in advance,

Best Regards,

Kiran

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Xilinx Employee
Xilinx Employee
17,630 Views
Registered: ‎11-28-2007

Re: PLL IP core for Spartan6 low power FPGAs

Jump to solution

I would suggest you open a web case with the technical support and ask what current status is. Often times it's pending characterization when moving a core from pre-production to production status.

 


@kchalla wrote:

Hi,

Can anyone please tell me when can be used the clocking wizard 3.2 to generate PLL in Spartan 6 Low Power FPGAs ?? For reference please refer to the above messages.

Is this due to Hardware restrictions or IP core problem?

Thanks in advance,

Best Regards,

Kiran




Cheers,
Jim

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Newbie amit1987
Newbie
11,731 Views
Registered: ‎09-24-2013

Re: PLL IP core for Spartan6 low power FPGAs

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Hi 

 

I am using Device Primitive Instatiation for PLL in Spartan-6. 

 

PLL_BASE: Phase Locked Loop (PLL) Clock Management Component

-- Spartan-6
-- Xilinx HDL Language Template, version 14.2

PLL_BASE_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
CLKFBOUT_MULT => 1, -- Multiply value for all CLKOUT clock outputs (1-64)
CLKFBOUT_PHASE => 0.0, -- Phase offset in degrees of the clock feedback output
-- (0.0-360.0).
CLKIN_PERIOD => 0.0, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
CLKOUT0_DIVIDE => 1,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLK_FEEDBACK => "CLKFBOUT", -- Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
COMPENSATION => "SYSTEM_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
REF_JITTER => 0.1, -- Reference Clock Jitter in UI (0.000-0.999).
RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
)
port map (
CLKFBOUT => CLKFBOUT, -- 1-bit output: PLL_BASE feedback output
-- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1,
CLKOUT2 => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
LOCKED => LOCKED, -- 1-bit output: PLL_BASE lock status output
CLKFBIN => CLKFBIN, -- 1-bit input: Feedback clock input
CLKIN => CLKIN, -- 1-bit input: Clock input
RST => RST -- 1-bit input: Reset input
);

-- End of PLL_BASE_inst instantiation

 

Can you please help me to understand how CLKFBOUT_MULT is used in PLL and hwo to decide its value

 

Thanks 

Amit Khare 

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Newbie tirpitz.me
Newbie
2,855 Views
Registered: ‎01-30-2018

Re: PLL IP core for Spartan6 low power FPGAs

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Hi Jim,
I need a PLL for DC baseband, and I found that this PLL's lowest input clock frequence is 6.125MHz, I wonder if there is a PLL IPcore that I can use.
Thanks,
Ben
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