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fpga_newbie
Observer
Observer
7,217 Views
Registered: ‎01-20-2012

PLL clock gating

I want to use a PLL with 250Mhz output w BUFG and a 500Mhz output w BUFPLL.   Both have a defined phase shift with regards to the pll inclk of 250Mhz.   I would simply like to "and" the two signals, but since they are part of the Spartan 6 global clocking network, it looks like that is a no-no.  That "and" output doesn't go to a pad, it will be used internally.  I would assume there are ways to use global clocks as part of the Spartan 6 fabric logic, but at this point I haven't found out how to take advantage of global clock resources for D inputs or gating logic?  I would assume clock forwarding would only be used when routing a signal to a pad?  Thanks in advance.

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eteam00
Instructor
Instructor
7,216 Views
Registered: ‎07-21-2009

A 500MHz clock, or a pulse formed from a 500MHz clock, exceeds the operating limits of the Spartan-6 BUFG global clock buffer.  The 500MHz clock is limited to the IO region.

 

-- Bob Elkind

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fpga_newbie
Observer
Observer
7,214 Views
Registered: ‎01-20-2012

Thanks for pointing that out, I now see that in DS162.   So to do something at that speed, I need to use the

High Speed I/O Clock Region only?  So is it safe to assume any synthesis needs to be based on IOTILE logic in the same region?

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eteam00
Instructor
Instructor
7,207 Views
Registered: ‎07-21-2009

So to do something at that speed, I need to use the  High Speed I/O Clock Region only?  So is it safe to assume any synthesis needs to be based on IOTILE logic in the same region?

 

Correct.  And the logic available to you has a very limited and specialised set of capabilities.  You may want to consider an alternate implementation which can be performed at a lower frequency word rate, in the fabric logic.

 

You call yourself "fpga_newbie".  Designing near the technology limits is not fun.  It is tedious and frustrating.  It's not a good place to be for a newbie.

 

-- Bob Elkind

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fpga_newbie
Observer
Observer
7,203 Views
Registered: ‎01-20-2012

"You call yourself "fpga_newbie". Designing near the technology limits is not fun. It is tedious and frustrating. It's not a good place to be for a newbie."

 

I'm new to Xilinx, Spartan 6's and Verilog, but not new to FPGAs......  Still tedious and frustrating, as the Spartan 6 is a different device than what I'm used too.   But the job at hand requires a faster device, and companies push to get a job done......

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eteam00
Instructor
Instructor
7,199 Views
Registered: ‎07-21-2009

Message received and understood.  Let us know if we can be of further service.

 

-- Bob Elkind

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fpga_newbie
Observer
Observer
7,195 Views
Registered: ‎01-20-2012

You are being "TONS OF HELP" and it is very much appreciated. Thanks
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eteam00
Instructor
Instructor
7,192 Views
Registered: ‎07-21-2009

I'm having trouble envisioning how you would use a 250MHz 25% duty cycle pulse in the fabric logic.

 

  • If it is to be used as a clock, a conventional 250MHz 50% should suffice.
  • If it is not used as a clock, what clock would "handle" this non-clock signal?

If you described what you are trying to design, maybe we can figure something out, together.

 

-- Bob Elkind

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fpga_newbie
Observer
Observer
7,186 Views
Registered: ‎01-20-2012

Part of it is just coming up to speed on the Spartan 6. 

 

But the actual need is an interface to a sensor, parallel data out (depending on sensor 5 bits to 15 bits).  The sensor also has a synchronous clock output that can be delay programmed to allow for data settling relative to the senor data output.  All outputs are LVDS.  Clock frequency is near 250Mhz, data out is DDR so near 500Mhz data rate.   Essentially have to store sensor outputs at the clk frequency in block ram when told to store.  Data length isn't long by today's standards 136 deep (by sensor width).

 

My plan was to use the input DDRs of the Spartan 6 to bring the write data rate down the the 250Mhz mark, use a PLL to sync to the clk and double it to derive block memory timing.  Target would try to get it into a -2 speed Spartan 6. 

 

I've read a few threads on ADCs here as data transactions are very similar.  Sensor data is proprietary.

 

Thanks in advance for any thoughts.

 

 

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eteam00
Instructor
Instructor
7,181 Views
Registered: ‎07-21-2009

The sensor also has a synchronous clock output that can be delay programmed to allow for data settling relative to the sensor data output.

 

Is the sensor output clock constantly running?  If not, then PLL is a no-go.

 

Clock frequency is near 250Mhz, data out is DDR so near 500Mhz data rate.   Essentially have to store sensor outputs at the clk frequency in block ram when told to store.  Data length isn't long by today's standards 136 deep (by sensor width).  My plan was to use the input DDRs of the Spartan 6 to bring the write data rate down the the 250Mhz mark, use a PLL to sync to the clk and double it to derive block memory timing.

  • De-muxing at 1:2 gives you a 250MHz fabric clock rate.  This is doable, but "fun" in Spartan-6.
  • De-muxing at 1:4 gives you a 125MHz fabric clock rate.  This isn't "fun", it would be downright "boring".
  • You lost me at "double it (the clock) to drive block memory timing".  If fabric runs at 250MHz, the BRAM would also be 250MHz.

If the source-synchronous skews from the sensor are low enough, you can use the PLL as a zero-delay buffer to regenerate the sampling clock for the input data.  In deserialisation, there is no advantage to using IDDR2 (with DDR clock) vs. ISERDES2 (using 1x SDR clock).  They are equivalent.  If you are going to use ISERDES2,  1:4 deserialisation is simple as 1:2 deserialisation.  Iin other words, 1:4 deserialisation in ISERDES2 is as simple as 1:2 deserialisation using IDDR2.

 

If the source-synchronous skews from the sensor are not low enough, then you'll want to use the IDELAY2 blocks in differential phase adjust mode, where the IDELAY2 blocks dynamically deskew input data relative to the sampling clock.

 

If you use the IDELAY2 approach, you don't need the PLL... but the input clock still needs to be constantly running.  The IDELAY2 blocks do not re-acquire clock lock instantaneously after dead stop re-start.

 

Does this make sense?

 

-- Bob Elkind

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fpga_newbie
Observer
Observer
6,906 Views
Registered: ‎01-20-2012

  

"Is the sensor output clock constantly running?  If not, then PLL is a no-go."   Essentially yes, the FPGA will start the sensor clock once configured. 

 

"De-muxing at 1:4 gives you a 125MHz fabric clock rate.  This isn't "fun", it would be downright "boring" in other words, 1:4 deserialisation in ISERDES2 is as simple as 1:2 deserialisation using IDDR2."

 

I'm starting to think thats what I need to do, seems like some of the timing results are close but I don't want to drive myself more nuts than I have to at this point.... 

 

"If the source-synchronous skews from the sensor are not low enough, then you'll want to use the IDELAY2 blocks in differential phase adjust mode, where the IDELAY2 blocks dynamically deskew input data relative to the sampling clock."  They will delay to a full clock cycle plus.

 

 

"Does this make sense?"  Yes at this point, but I'm sure in a few hours or a day, something else will confuse me.....

 

Thanks

 

 

 

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eteam00
Instructor
Instructor
6,902 Views
Registered: ‎07-21-2009

"If the source-synchronous skews from the sensor are not low enough, then you'll want to use the IDELAY2 blocks in differential phase adjust mode, where the IDELAY2 blocks dynamically deskew input data relative to the sampling clock."  They will delay to a full clock cycle plus.

 

That's half of it -- the range of timing adjustment between the clock output and the data output.

 

The other half is the stability of the timing relationship between the clock output and the internal (1x) clock over process (manufacturing lot), temp, and voltage.

 

The 3rd half is the  min/max clock (internal 1x clock) => output delay from the data sheet.  This establishes the 'data valid' window width.

 

There you have it -- all three halves of the problem.

 

-- Bob Elkind

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fpga_newbie
Observer
Observer
6,897 Views
Registered: ‎01-20-2012

"The other half is the stability of the timing relationship between the clock output and the internal (1x) clock over process (manufacturing lot), temp, and voltage."

 

"The 3rd half is the min/max clock (internal 1x clock) => output delay from the data sheet. This establishes the 'data valid' window width."

 

Assuming there is no FPGA PLL, and the sensor clock stability is a known low jitter clock source :  I'm not sure I'm following your statements.  If you mean the FPGA manufacturing lot/temp/voltage for clock path delay to ISERDES clk/data, won't that come out of the timing analysis?  Or do you mean something else?

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eteam00
Instructor
Instructor
6,891 Views
Registered: ‎07-21-2009

You have to be careful, because the sensor is proprietary, right?

 

Here is an example of the numbers you might derive from the datasheet, pulled out of thin air.

 

There is an internal clock signal which is the timing reference for the two outputs from the sensor:

  • half_clock
  • ddr_data

 

Specs:

 

                    description      min        max

              clock to ddr_data       0       0.25nS

            clock to half_clock       0       0.25nS

        half clock delay adjust       0       4.0 nS

half_clock delay (from nominal)    -125pS     +125ps

 

The reasons that the min and max delay specs are not identical are because of variations in:

  • P -- process (manufacturing lot)
  • V -- voltage
  • T -- die temperature

The timing diagrams do NOT take into account that the ddr_data delays should track the half_clock delays, because the PVT factors are the same for both types of signals.  So these diagrams represent an unrealistically pessimistic application of the example datasheet specifications.

          _____       _____       _____       _____       _____       _____     

clock  __/     \_____/     \_____/     \_____/     \_____/     \_____/     \___
                  _________   _________   _________   _________   _________   ___

ddr_data       XXX_________XXX_________XXX_________XXX_________XXX_________XXX___

                  _________               _________               _________     

half_clock(1)  ///         \\\_________///         \\\_________///         \\\___

                          ______                  ______                  ______     

half_clock(2) ______//////      \\\\\\______//////      \\\\\\______//////      \\\\\\

 

The crude timing diagrams are actually more or less to scale.  Note the narrow timing margin between the

ddr_data transitions and the (delayed) half_clock edges, after accounting for cumulative delay uncertainties.

 

The timing margins are reduced further by

  • circuit board interconnect skews
  • clock buffer and distribution skews in the FPGA
  • the required data setup and hold times relative to the (distributed) on-chip sampling clock

Does this make sense?

 

-- Bob Elkind

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4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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fpga_newbie
Observer
Observer
6,887 Views
Registered: ‎01-20-2012

I see your points.

 

I forgot to mention, this isn't a full bore production type design.   Used in house only, the end product FPGA count is a handfull, I can tweak ......although my preference is to not need to tweak.  I'm targeting the -2 speed to fall back on faster if in the end it is needed.

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bassman59
Historian
Historian
6,876 Views
Registered: ‎02-25-2008


@fpga_newbie wrote:

Part of it is just coming up to speed on the Spartan 6. 

 

But the actual need is an interface to a sensor, parallel data out (depending on sensor 5 bits to 15 bits).  The sensor also has a synchronous clock output that can be delay programmed to allow for data settling relative to the senor data output.  All outputs are LVDS.  Clock frequency is near 250Mhz, data out is DDR so near 500Mhz data rate.   Essentially have to store sensor outputs at the clk frequency in block ram when told to store.  Data length isn't long by today's standards 136 deep (by sensor width).

 

My plan was to use the input DDRs of the Spartan 6 to bring the write data rate down the the 250Mhz mark, use a PLL to sync to the clk and double it to derive block memory timing.  Target would try to get it into a -2 speed Spartan 6. 

 

I've read a few threads on ADCs here as data transactions are very similar.  Sensor data is proprietary.

 

Thanks in advance for any thoughts.

 

 


One question ... is the sensor output serial or parallel? If it's serial and needs to be deserialized, your job is somewhat (hah) simplified because once the data are deserialized, your "parallel" (deserialized) clock rate is a fraction of the serial data rate. So pushing the word-length data into a memory is pretty easy.

 

If you have to handle parallel data at 250 MHz DDR, then things get a little bit more difficult.

----------------------------Yes, I do this for a living.
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eteam00
Instructor
Instructor
6,875 Views
Registered: ‎07-21-2009

is the sensor output serial or parallel?

 

Parallel data output, see post #9 in this thread.

 

-- Bob Elkind

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fpga_newbie
Observer
Observer
6,864 Views
Registered: ‎01-20-2012

I'm still debating clock and data structure.  See the attached block.  Where I'm getting stuck is still clock routing.  I'd like to try using the DCM to generate several clock outputs as well as align the incoming clock.  Part of it maybe relying on the core generator too much. Eventually I need to route to data to bram and a magnitude comparitor.  I realize I'm pushing timing, but for now I'd just like to get a model to work with using DDR instead of ISERDES even at a slower clock frequency......

 

Thanks

sblock.png
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eteam00
Instructor
Instructor
6,859 Views
Registered: ‎07-21-2009

See the attached block.  Where I'm getting stuck is still clock routing.

 

Your diagram looks good, except that only a PLL can drive the BUFPLL input.  If you replace the "PLL/DCM" with a PLL, the diagram looks good.

 

Using a PLL, you should have no clock routing problem, unless the assigned clock input pin is an awkward selection (i.e. can't drive a BUFIO2 from this pin).  It would help if you posted your code which embodies the diagram, plus any error messages you may be seeing.

 

-- Bob Elkind

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fpga_newbie
Observer
Observer
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Registered: ‎01-20-2012

I'm starting to get there.  Looks like I really need to just accept that the core generator output needs tweaking periodically to tailor buffering.  I don't seem to get enough questions from the wizzard.

 

 I do have a Verilog question, using the core generator configured differential input pins and a DDR bus :  So if data in pins are 4 differential data signals (8 pins), the DDR data out put is 8 data lines (X_DATA below).  To split the Q0 and Q1 data, is there a syntax way that I can replace X_DATA (from DATA_IN_TO_DEVICE) into the deserialize data stream?  i.e. X_DATA_A[3:0] and X_DATA_B[3:0] where X_DATA_A is the Q0 outputs of the DDR, and X_DATA_B is the Q1 outputs.

 

  IN_DDR X_IN
   (
  // From the system into the device
    .DATA_IN_FROM_PINS_P(DATA_IN_FROM_PINS_P),
    .DATA_IN_FROM_PINS_N(DATA_IN_FROM_PINS_N),
    .DATA_IN_TO_DEVICE(X_DATA),
    .CLK_IN(UX_CLK_OUT1),
    .CLK_OUT(xxCLK_OUT),
    .CLK_RESET(CLK_RESET),
    .IO_RESET(IO_RESET)
);

 

Much thanks again.

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

Looks like I really need to just accept that the core generator output needs tweaking periodically to tailor buffering.  I don't seem to get enough questions from the wizard.

 

Please be specific.

  • What does "core generator output needs tweaking periodically to tailor buffering" mean?
  • What questions are missing from the wizard?

 

To split the Q0 and Q1 data, is there a syntax way that I can replace X_DATA (from DATA_IN_TO_DEVICE) into the deserialize data stream?

 

I don't understand what you are trying to do.  What does "replace <signame> into the deserialize data stream" mean?

 

i.e. X_DATA_A[3:0] and X_DATA_B[3:0] where X_DATA_A is the Q0 outputs of the DDR, and X_DATA_B is the Q1 outputs.

 

This is straightforward.  Have you seen the IDDR2 primitive template?

 

Your simplest coding strategy is to explicitly instantiate IBUFDS differential input buffers and IDDR2 input registers.  You don't earn any extra designer points by avoiding the use of instantiated primitives, or by reducing the lines of source code to a bare minimum.

 

If you are trying to parameterise the width of the IBUFDS/IDDR2 datapath, this is fairly simple to do.  Knock yourself out!

 

-- Bob Elkind

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