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8,090 Views
Registered: ‎09-10-2015

PLL from FMC input on Spartan-6 LX150T

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Hello all,

 

I am new to both this forum and Xilinx devices/design software, but have some experience with Altera devices/design software.

 

At the moment I am trying to design a cameralink interface. In order to do this I have a connector attatched to an FMC connector of a Spartan-6 LX150T. However this gives me some trouble that I don't understand and I hope some of you may be able to help me on my way.

Am I correct in thinking I can use the core generator to generate both the required PLL and SERDES?

I tried this for the PLL only and got the error "ERROR:NgdBuild:604 - logical block **/**/plle2_adv_inst' with type
   'PLLE2_ADV' could not be resolved. A pin name misspelling can cause this, a
   missing edif or ngc file, case mismatch between the block name and the edif
   or ngc file name, or the misspelling of a type name. Symbol 'PLLE2_ADV' is
   not supported in target 'spartan6'."

A search on this forum did not help me solve the problem. I did read something about the placement of input clocks and the PLL/DCM tiles, but does this mean I cannot use the FMC?

 

Any help will be greatly appreciated.

 

Oh, and before you ask: I use ISE 14.7.

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15,308 Views
Registered: ‎09-10-2015

Found I did't add ALL the correct files to the project.

For others having similar problems: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_coregen_ip.htm

View solution in original post

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Xilinx Employee
Xilinx Employee
8,082 Views
Registered: ‎08-01-2008
Unfortunately we do not provide any sort of Camera link core. The closest thing we have is the Select-IO Wizard which sets up the FPGA IOs for the Camera Link interface. Note that the Select-IO wizard is only supperted for 6-series and newer devices.
Have the customer refer to their FAE in regards to what third party cores and vendors they need for their design.
Thanks and Regards
Balkrishan
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8,077 Views
Registered: ‎09-10-2015

Hallo Balkrishan,

 

I am not iterested in a cameralink core, but in a tip to help me implement the PLL core from the core generator. I can't find relevant information on the error 604, which I also get when trying to implement the serdes via the selectIO wizard.

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Xilinx Employee
Xilinx Employee
8,074 Views
Registered: ‎08-01-2008

This error come if any library or module missing in your design. You may share your design or check yourself at your end

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.
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Highlighted
15,309 Views
Registered: ‎09-10-2015

Found I did't add ALL the correct files to the project.

For others having similar problems: http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_using_coregen_ip.htm

View solution in original post

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