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Observer
Observer
8,391 Views
Registered: ‎01-24-2010

PLL reset mechanism with MDM

Running a custom Spartan-6 board. I'm wondering what the proper mechanism is for resetting a PLL when the system is reprogrammed via JTAG and ultimately reset using the MDM after programming of a MicroBlaze. Should the PLL reset signal be connected directly to the Debug_SYS_Rst output of the MDM? We're seeing what appears to be random startup problems where the MicroBlaze stalls reading from DRAM and are thinking its related to the DRAM clocks not coming out of reset correctly.

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Moderator
Moderator
8,351 Views
Registered: ‎02-16-2010

If you do not need to reset PLLs again after programming the FPGA, you can have a soft logic which is enabled upon completion of config and reset the PLL once as per the reset requirement of PLL.
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