08-07-2017 04:33 AM
I have a Place:1108 error caused by a signal clocking an internal SPI core that I don't really understand.
My device is XC6SLX4_TQG144
I have the following map error:
ERROR:Place:1108 - A clock IOB / BUFGMUX clock component pair have been found that are not placed at an optimal clock IOB / BUFGMUX site pair. The clock IOB component <spi_clk_i> is placed at site <P70>. The corresponding BUFG component <spi_clk_i_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is only a select set of IOBs that can use the fast path to the Clocker buffer, and they are not being used. You may want to analyze why this problem exists and correct it. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "spi_clk_i" CLOCK_DEDICATED_ROUTE = FALSE; >
The spi_clk_i signal is on P70 (1MHz).
The other clock in the design is the main sync clock on P133 (20MHz).
Here are the corresponding .ucf constraints:
NET "clk20mhz_i" LOC = P133 | IOSTANDARD = LVCMOS33 | PERIOD = 40 ns; NET "spi_clk_i" LOC = P70 | IOSTANDARD = LVCMOS33 | PERIOD = 1 us;
The workaround we used to avoid this error was to sync the spi_clk with the main clock, something like:
if rising_edge(clk20mhz_i) spi_clk_reg <= spi_clk_i; ...
and then use spi_clk_reg as the SPI clock.....
If I add the CLOCK_DEDICATED_ROUTE constraint, the error is demoted to a warning as described (whether I set it to TRUE or FALSE..?!).
I don't really understand why this error is occurring, even though I suppose the pin selection for spi_clk_i is bad.
Could somebody please explain why this is happening ?
What are the risks of using the CLOCK_DEDICATED_ROUTE constraint, and what is the difference between setting it to FALSE or TRUE (seems to produce the same results) ?
If I had to redesign the board, what would be a better pin selection and why?
Any help would be very appreciated, thanks.
08-07-2017 04:37 AM - edited 08-07-2017 04:39 AM
The problem with using CLOCK_DEDICATED_ROUTE constraints is that you can end up with a large variable delay in the path from the input buffer (IBUFGDS in your case) to the clock buffer (BUFGMUX). If your design has appropriate setup and hold timing constraints (offset in before) to each of the input clocks, you can check whether you still meet timing. Usually adding delay to clocks will result in input hold timing violations, and these do not depend on the clock frequency since hold time is measured to the same clock edge and does not involve the clock period
you have to pick specific pin pairs that have independent routing channels to the same BUFGMUX. If you have already built your hardware and can't change the pinout, then you may need to live with the CLOCK_DEDICATED_ROUTE constraint and its associated timing issues. Then you need to figure out how to work around any system-level timing issues like input hold time.
08-07-2017 06:26 AM
Thanks for your quick answer. I'm still a bit confused, sorry, noob here...
What do you mean by "large variable delay"?
I didn't set any particular setup and hold timing constraints. Should I still worry if I don't get any error in Timing reports ? BTW, I don't get any issue either when testing the hardware.
Also, could you give me an example of a better pin selection, and tell me why it is better than P70 ?