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Explorer
Explorer
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Registered: ‎11-28-2011

Planning Clock Network on Spartan 6 LX75T device

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I've read through UG382 and have some questions regarding the overall clock network. 

Is it possible for all of the FPGA logic to share the same Global clock through two global clock input pins?

Let's say my CCA is providing two differential pins to the FPGA via GCLK4/5. Is it possible from the entry of only these two pins that clocking can be provided to all of the banks?

 

From what I am interpreting, it seems that if the clock comes in on GLK4/5, I can use two BUFIO2's (or one BUFPLL?) to distribute the clock throughout Bank1 (to span regions RT and RB). How do I get the clock to the other banks? Would I have to have my external clock come into the FPGA on multiple GCLK pins, or can this distribution be done internally?

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Scholar
Scholar
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Registered: ‎02-27-2008

p,

 

"Global" = goes to every IO and every CLB.

 

So yes, one global clock (BUFG) may be distributed to all flip flops in the IOB and CLB.

 

One has to come in on a IBUFG - any one of the dedicated clock input IOB's (and differential inputs use two pins from two IOB's).

 

Once on the chip, all global clock capable input pins go to a switch in the center for distribution.

 

BUFIO and other resources are not global.  They have restrictions on where they go.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Scholar
Scholar
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Registered: ‎02-27-2008

p,

 

"Global" = goes to every IO and every CLB.

 

So yes, one global clock (BUFG) may be distributed to all flip flops in the IOB and CLB.

 

One has to come in on a IBUFG - any one of the dedicated clock input IOB's (and differential inputs use two pins from two IOB's).

 

Once on the chip, all global clock capable input pins go to a switch in the center for distribution.

 

BUFIO and other resources are not global.  They have restrictions on where they go.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

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Explorer
Explorer
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Registered: ‎11-28-2011

Austin,

I guess I was confused by the verbage:

"All SelectIO logic resources (input registers, output registers, IDDR2, ODDR2, ISERDES2,
and OSERDES2) must be driven by a clock coming from either a BUFIO2 located within
the same BUFIO2 clocking region, one of the BUFPLLs on the same edge of the device, or
one of the 16 BUFGs."

 

and the following section

Spanning a Full Bank with a Single Global Clock Input With Two I/O Clocks

 

So when what is the true purpose of the BUFIO2's, as illustrated in Figure 1-7? Purely for DCM's, PLL's, and registers around the periphery?

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Scholar
Scholar
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Registered: ‎02-27-2008

When you run out of BUFG,


You will need more clocking resources, so we provide local clocks for those designs that use up all the global resources.  The IO clocks are used with the IOSERDES blocks, so they are convenient there, as those functions are for a few pins only, and it would be wasteful to dedicate a global resource for just a few pins.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Historian
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Registered: ‎02-25-2008

@polyee13 wrote:

 

So when what is the true purpose of the BUFIO2's, as illustrated in Figure 1-7? Purely for DCM's, PLL's, and registers around the periphery?


The BUFIO2 clock networks have a much smaller prop delay from pad to network than a clock on a BUFG. So for fastest performance (say, deserializing a fast DDR data line) you need to use the BUFIO2.

 

Consider an edge-aligned DDR source-synchronous data/clock connection between some source and your FPGA. This means that the clock edge occurs with each data edge. In the FPGA, your path from the data input pad to the ISERDES or IDDR element is very short. But the path from the clock input pad to the global clock (BUFG) buffer then distributed out back to the IOB is fairly long. If that time is excessive, which is basically defined by clock period, then you can't reasonably capture your input data. So the BUFIO2 comes into play. Since it's distributed to a much smaller part of the device than a global clock buffer, its path length is much shorter.

 

 

----------------------------Yes, I do this for a living.
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