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Visitor ssss
Visitor
9,260 Views
Registered: ‎06-19-2008

Please help me / Spartan-3 I/O Standards


Hello,

I built an PCB Board with a Spartan 3 FPGA (XC3S1000FG456).
All VCCO Pins (all banks) are connected to a 3,3V power supply.

I would like to use the Pins B4 (IO / L01P_0 / VRN_0) and A3 (IO / VRef_0) as a Single End Input Output with LVTTL (3,3V) Standard.

My problem is: I use Altium Designer and get a compiling error.
The error message is meant that this pins can not use with the LVTTL Standard

In which Single End I/O Standard can I use the I/O-L01P_0-VRN_0 Pin, in the case of VCCO_0...VCC_7 is 3,3 Voltage?
What happens when I configure an I/O Pin as LVCMOS25 (2,5V) (in the constraints of the FPGA Program) and I connect all VCCO to 3,3 Voltage?

Many thanks
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4 Replies
Highlighted
Instructor
Instructor
9,160 Views
Registered: ‎08-14-2007

Re: Please help me / Spartan-3 I/O Standards

LVCMOS25 and LVCMOS33 are not very different and will probably work fine with the wrong Vcco voltage.  However the timing reports will not properly characterise these mis-matched voltage / drive combinations. Also the assumption that the Vcco is 2.5V will prevent you from specifying 3.3 volt standards in the same bank.

 

For newer parts, the default I/O standard is LVCMOS25.  If your Vcco is tied to 3.3V you should add the IOStandard attribute for each pin in your ucf file.  You can add the attribute at the end of the LOC constraint line using a vertical bar like:

NET "net_name"  LOC = "B4" | IOSTANDARD = LVCMOS33;

 

Once you have identified all of your other I/O as 3.3V based, there should be no error when you assign some pins to LVTTL.

 

HTH,

Gabor 

-- Gabor
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Visitor ssss
Visitor
9,130 Views
Registered: ‎06-19-2008

Re: Please help me / Spartan-3 I/O Standards

I am very happy,

 All dual purpose pins are 3,3V tolerant with the dedicated bank VCCO=3,3V.

With Xilinx tools I could assign the LVTTL standard to dual purpose pins.

There is an error in the Altium Designer. 

 

Thank you

Message Edited by ssss on 06-20-2008 01:52 AM
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Explorer
Explorer
6,109 Views
Registered: ‎11-13-2007

Re: Please help me / Spartan-3 I/O Standards

This message is a little old now, but how do you know the error is with Altium Designer?

Maybe you didn't define something correctly?? The error checking for I/O standards is not done in Altium Designer, it's done in Xilinx tools.

Altium Designer passes a ton of project info to Xilinx, and possibly you didn't set up the Altium constraint file properly, so it could pass the info to Xilinx.

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Visitor ssss
Visitor
6,088 Views
Registered: ‎06-19-2008

Re: Please help me / Spartan-3 I/O Standards

Hi,

I used Altium Designer 6.9. I did the whole design-process (Schematic / PCB and VHDL-FPGA-Design) with Altium Designer. First I drew the schematics and some signal name were defined as inverted Signals. Therefore I put before every letter a slash or backslash in my schematics. Like "/O/E/N" or "\O\E\N". The schematic translates this signal name in the name OEN with a line above  the name. Unfortunately the slash or backslash is not allowed in signal names in the VHDL language. Therefore Altium Designer remove the slashes in the VHDL-FPGA-Design. I believe there were some inconsistency between constrains file  and VHDL top sheet by the compiling process. I removed all slash and backslash. After that I did not get any error like mentioned. I will never use slash or backslash in my signal names anymore.

Michael 

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