06-19-2008 05:07 AM
06-19-2008 06:26 AM
LVCMOS25 and LVCMOS33 are not very different and will probably work fine with the wrong Vcco voltage. However the timing reports will not properly characterise these mis-matched voltage / drive combinations. Also the assumption that the Vcco is 2.5V will prevent you from specifying 3.3 volt standards in the same bank.
For newer parts, the default I/O standard is LVCMOS25. If your Vcco is tied to 3.3V you should add the IOStandard attribute for each pin in your ucf file. You can add the attribute at the end of the LOC constraint line using a vertical bar like:
NET "net_name" LOC = "B4" | IOSTANDARD = LVCMOS33;
Once you have identified all of your other I/O as 3.3V based, there should be no error when you assign some pins to LVTTL.
06-20-2008 01:50 AM - edited 06-20-2008 01:52 AM
I am very happy,
All dual purpose pins are 3,3V tolerant with the dedicated bank VCCO=3,3V.
With Xilinx tools I could assign the LVTTL standard to dual purpose pins.
There is an error in the Altium Designer.
07-16-2009 02:13 PM
This message is a little old now, but how do you know the error is with Altium Designer?
Maybe you didn't define something correctly?? The error checking for I/O standards is not done in Altium Designer, it's done in Xilinx tools.
Altium Designer passes a ton of project info to Xilinx, and possibly you didn't set up the Altium constraint file properly, so it could pass the info to Xilinx.
07-17-2009 11:20 AM
I used Altium Designer 6.9. I did the whole design-process (Schematic / PCB and VHDL-FPGA-Design) with Altium Designer. First I drew the schematics and some signal name were defined as inverted Signals. Therefore I put before every letter a slash or backslash in my schematics. Like "/O/E/N" or "\O\E\N". The schematic translates this signal name in the name OEN with a line above the name. Unfortunately the slash or backslash is not allowed in signal names in the VHDL language. Therefore Altium Designer remove the slashes in the VHDL-FPGA-Design. I believe there were some inconsistency between constrains file and VHDL top sheet by the compiling process. I removed all slash and backslash. After that I did not get any error like mentioned. I will never use slash or backslash in my signal names anymore.