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Observer amirsadegh
Observer
1,618 Views
Registered: ‎08-03-2018

Problem with DCM HDL design in Spartan 6

Hi 

I am new in forum .

I have a problem with DCM HDL design in Spartan 6 . When i want to use this HDL design instantiation template (Verilog Instantiation Template) in UG615 Doc  named "Spartan-6 Libraries Guide for HDL Designs" an erroe occur in iplementation part : 

ERROR:Pack:198 - NCD was not produced. All logic was removed from the design.
This is usually due to having no input or output PAD connections in the
design and no nets or symbols marked as 'SAVE'. You can either add PADs or
'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in
the mapper. For more information on trimming issues search the Xilinx
Answers database for "ERROR:Pack:198" and read the Master Answer Record for
MAP Trimming Issues.

What should i do ??

Is there any way to use "DCM_SP" primitive ??

Is there any DCM IP_Core ??

I did not find any IP_Core in ISE and when i search it says your devise dose not support this IP_core...

I use XC6SLX9.

thank you.

 

 

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21 Replies
Voyager
Voyager
1,591 Views
Registered: ‎03-28-2016

Re: Problem with DCM HDL design in Spartan 6

For Spartan 6, you can open "CORE Generator" and look for the "Clocking Wizard".  From there you can generate a customized clocking IP.

 

In any case, the errors that you are seeing are because all of the logic has been optimized away.  This happens when some or all of an IP's inputs or outputs are not connected to anything valid.  For instance, the DCM has to have a clock input to drive it.  The clock input has to be from a pin on the FPGA or from some other clock source inside the chip.  The DCM also must drive something with it's output clock.  That could be some logic in the FPGA fabric or it could be an output pin on the FPGA.  Any logic in the design that is not driven by proper inputs or does not drive proper outputs will be removed from the design by the software.

Ted Booth - Tech. Lead FPGA Design Engineer
www.designlinxhs.com
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Observer amirsadegh
Observer
1,583 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

Hi 

Thank you very much for your answer...

Actually i was looking for something that i can shifting a signal for example 45 degree. Then i found that DCM  can do it because it has "Variable phase shift operation" . 

Is there any way to shift a signal ??  i need Variable phase shift 

This is my main goal to shift a signal 

thank you

0 Kudos
1,579 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

A DCM can phase shift a continuously running clock.  It cannot phase shift a non-continuous or aperiodic signal.  When you are saying "signal" do you mean a single bit or do you mean something like phase shifting a bus that represents something like a sine wave?

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Observer amirsadegh
Observer
1,569 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

Hi 

Thank you for your answer...

I mean a single bit and non_continuous signal . It is NOT a clock . 

thank you

pic.png
0 Kudos
1,562 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

By how much time are you trying to shift it and what clocks do you have available in your design?

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Observer amirsadegh
Observer
1,552 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

My devise is XC6SLX9 and i want to use best speed but i dont know . I need variable phase-shifting.

What to you suggest ??

Is it possible to make it ??

0 Kudos
1,524 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

Unless your signal is a clock, that is unless it is periodic and fits in the frequency and duty cycle requirements of a PLL, DCM or MMCM construct, you should stop thinking of this as a phase shift and think of this as a time delay.  What resolution do you need on the delay, 1 nS, 5nS, 1 uS?  What is the maximum range of time that you need to delay this signal?

Observer amirsadegh
Observer
1,510 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

Hi 

I was waiting for your help ... 

Yes , you are right . I think delay is a good word insted of  phase shift . 

1ns is enough . what should i do now ??

Thank you ... 

0 Kudos
1,497 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

Are you trying to delay a signal for use in your FPGA or are you trying to bring is a signal, delay is by a nS and then send it back out?  If the latter, an FPGA is a poor choice.  Even if you bring a signal in and send it out an adjacent pin, you may get more than 1nS of delay.  This delay will be sensitive to process, voltage and temperature (PVT) variations.  If you just want to delay a signal for use in the FPGA, there is the IDELAY primitive.

 

A quick check of Digikey isn't finding any short period, variable delay lines.  This may sound kind of crude, but can you try running your signal through various lengths of coax?

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Observer amirsadegh
Observer
1,482 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

No no no ... 

My signal comes into FPGA then i want to delay it and do some process .

 Do you mean IODELAY??

 

0 Kudos
1,471 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

Yes, IODELAY can be used to delay a signal by small amounts like you want.  Typically it is used to align an input signal with an input clock.  You are not showing a clock in your figure, so I'm not sure why you want a small delay. 

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Observer amirsadegh
Observer
1,464 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

Thank you 

I have another problem : 

What should i do if i want to convert this signal in FPGA ??

Any circuit ?

pic1.png
0 Kudos
1,458 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

How are you entering your design, with an RTL like verilog or VHDL, or some other method?

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Observer amirsadegh
Observer
1,449 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

Hi

I am using Verilog and i am new in FPGA ...

0 Kudos
1,442 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

Setting a signal high upon detection of a pulse is a fairly basic thing to do in an RTL like verilog.  I suggest that you try to code this and simulate it.  If you have problems with the design, a new post in Design Entry would be appropriate.  If you have trouble with the simulator, Simulation and Verification is the right forum.

Observer amirsadegh
Observer
1,429 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

Can you introduce me an ebook or booklet or ... about learning Verilog HDL ?? 

0 Kudos
1,425 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

I'm a VHDL guy.  If you Google verilog tutorial, you will get a couple hundred thousand hits.  The first two pages of results look pretty good.

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Observer amirsadegh
Observer
1,399 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

I have a external pulse as a trigger signal and i want to convert it to a continuous signal .

what should i do ?? 

I do not want to use PLL or DCM Because they need continuous signal  . So i should make an oscillator .

can you help me ?? 

Frequency is under 200MHZ.

Thank you ...

0 Kudos
1,387 Views
Registered: ‎06-21-2017

Re: Problem with DCM HDL design in Spartan 6

If you have a commercially available board it will have at least one oscillator on it connected to the FPGA.  Use it.  Connect the on-board oscillator to a DCM, use the DCM to produce a clock fast enough to capture your signal, synchronize your signal to this clock, then do whatever you need to do with the signal.

Observer amirsadegh
Observer
1,029 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

No no no 

Please read my last post carefully !! 

I should`t use PLL or DCM .

 

 

pic.png
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Observer amirsadegh
Observer
994 Views
Registered: ‎08-03-2018

Re: Problem with DCM HDL design in Spartan 6

I found it ..... 

Here is my solution ....

Thanks to me !!

 

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