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Visitor sekox
Visitor
6,397 Views
Registered: ‎02-07-2011

Problem with different clock domains

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Hi,

 

After reading lots of documents and countless tries I had to ask for your guidance.

 

I have a ZESTET1 Ethernet board with Spartan XCS1400A FPGA installed. This board has 1 Gbps ethernet interface and a TCP-IP offload engine. My main goal is to interface this  board with Analog devices AD9229 ADC, ADC has serial LVDS interface and a transfer rate of 480 Mbps. A DDR data clock and frame clock is generated for data capturing. ZESTET1 board runs at 125 MHz, but the data clock of ADC is 240 MHz so I am having trouble acquiring data and streaming it through ethernet card in real time. I tried using FIFO but I failed. Seriosuly I created a big mass. 

 

Any ideas and guidance are appreciated. Thanks for your time.

 

AD9229 Datasheet

ZestET1 

 

 

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Teacher rcingham
Teacher
8,230 Views
Registered: ‎09-09-2010

Re: Yet another system design problem

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"Does reading out in burst from fifo mean; using independent read and write clocks for fifo design?"

Yes. You will need a "data" clock domain, and a separate "Ethernet" clock domain, and the FIFO acts as the bridge between them. A standard good design practice.

Your caution regarding multiple clock domains is refreshingly sensible - and quite unlike some other newbie posters...

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"If it don't work in simulation, it won't work on the board."

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8 Replies
Teacher rcingham
Teacher
6,385 Views
Registered: ‎09-09-2010

Yet another system design problem

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First, a sanity check:
ADC data rate = 60Mbyte/s (40MS/s)
Ethernet data rate < 125Mbyte/s
You might make it work...

You do need to buffer up the ADC data in a FIFO, writing it continuously at the ADC rate, and reading it out in bursts for each frame. The 12-bit sample size definitely makes it more complicated - 2 samples = 3 bytes.

 

If you have to run any protocol on top of Ethernet it could be very tight on timing. TCP/IP is a real no-no. UDP over IP is just possible.

 


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"If it don't work in simulation, it won't work on the board."
Visitor sekox
Visitor
6,374 Views
Registered: ‎02-07-2011

Re: Yet another system design problem

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Thanks for quick reply,

 

I am also considering to use UDP as protocol. Does reading out in burst from fifo mean; using independent read and write clocks for fifo design? Because I am an inexperienced user; using more than one clock rate makes me seriosuly confused. I can write maximum of 64 Kbytes  data to ethernet outgoing fifo (this is the fifo in offload engine, I have no control over it). 

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Teacher rcingham
Teacher
8,231 Views
Registered: ‎09-09-2010

Re: Yet another system design problem

Jump to solution
"Does reading out in burst from fifo mean; using independent read and write clocks for fifo design?"

Yes. You will need a "data" clock domain, and a separate "Ethernet" clock domain, and the FIFO acts as the bridge between them. A standard good design practice.

Your caution regarding multiple clock domains is refreshingly sensible - and quite unlike some other newbie posters...

------------------------------------------
"If it don't work in simulation, it won't work on the board."

View solution in original post

Visitor sekox
Visitor
6,333 Views
Registered: ‎02-07-2011

Re: Problem with different clock domains

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Hi again,

 

I have simulated a FWFT FIFO with ISim  but I am pretty sure that something is wrong. My intention is to understand the behaviour of the fifo by inspecting the waveforms but the waveforms attached below does not make sense. I think fifo behaves wrong :Dfifo.JPG

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Teacher rcingham
Teacher
6,317 Views
Registered: ‎09-09-2010

Re: Problem with different clock domains

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The FIFO starting 'Full' does look odd. Are there any warning messages? (I have never used ISIM, so I don't know exactly where they would appear).

Also, are you using the Structural simulation model for the FIFO?


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"If it don't work in simulation, it won't work on the board."
Xilinx Employee
Xilinx Employee
6,300 Views
Registered: ‎11-28-2007

Re: Problem with different clock domains

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I assume this is an asynchronous FIFO. If yes, the default reset value of the FULL flag is one. You can change the FULL reset value in Coregen. Please check the "Reset Behavior" chapter in the FIFO Generator UG below (By the way, download Xilinx Document Navigator to manage all HW/SW/IP docs)

 

http://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v8_2/fifo_generator_ug175.pdf

 

 


@rcingham wrote:
The FIFO starting 'Full' does look odd. Are there any warning messages? (I have never used ISIM, so I don't know exactly where they would appear).

Also, are you using the Structural simulation model for the FIFO?




Cheers,
Jim
Visitor sekox
Visitor
6,296 Views
Registered: ‎02-07-2011

Re: Problem with different clock domains

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Thanks a lot for your both valuable comments, and document navigator seems to be seriously useful. I will try work out my problems, but unfortunately it looks like I will be giving you more trouble in following days :D
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Teacher rcingham
Teacher
6,293 Views
Registered: ‎09-09-2010

Re: Problem with different clock domains

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@jimwu wrote:

I assume this is an asynchronous FIFO. If yes, the default reset value of the FULL flag is one. You can change the FULL reset value in Coregen. 

[snip]



Gosh! I really hadn't noticed that before. And in the XCO file for my latest Async FIFO, it says:

CSET full_flags_reset_value=0

So, I probably just check the relevant box by instinct...

 


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"If it don't work in simulation, it won't work on the board."
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