07-14-2011 04:00 AM
After reading lots of documents and countless tries I had to ask for your guidance.
I have a ZESTET1 Ethernet board with Spartan XCS1400A FPGA installed. This board has 1 Gbps ethernet interface and a TCP-IP offload engine. My main goal is to interface this board with Analog devices AD9229 ADC, ADC has serial LVDS interface and a transfer rate of 480 Mbps. A DDR data clock and frame clock is generated for data capturing. ZESTET1 board runs at 125 MHz, but the data clock of ADC is 240 MHz so I am having trouble acquiring data and streaming it through ethernet card in real time. I tried using FIFO but I failed. Seriosuly I created a big mass.
Any ideas and guidance are appreciated. Thanks for your time.
07-15-2011 02:10 AM
07-14-2011 07:53 AM - edited 07-14-2011 07:55 AM
First, a sanity check:
ADC data rate = 60Mbyte/s (40MS/s)
Ethernet data rate < 125Mbyte/s
You might make it work...
You do need to buffer up the ADC data in a FIFO, writing it continuously at the ADC rate, and reading it out in bursts for each frame. The 12-bit sample size definitely makes it more complicated - 2 samples = 3 bytes.
If you have to run any protocol on top of Ethernet it could be very tight on timing. TCP/IP is a real no-no. UDP over IP is just possible.
07-14-2011 01:41 PM
Thanks for quick reply,
I am also considering to use UDP as protocol. Does reading out in burst from fifo mean; using independent read and write clocks for fifo design? Because I am an inexperienced user; using more than one clock rate makes me seriosuly confused. I can write maximum of 64 Kbytes data to ethernet outgoing fifo (this is the fifo in offload engine, I have no control over it).
07-15-2011 02:10 AM
07-17-2011 07:35 AM
07-18-2011 03:43 AM
07-19-2011 04:26 AM - edited 08-24-2011 05:12 AM
I assume this is an asynchronous FIFO. If yes, the default reset value of the FULL flag is one. You can change the FULL reset value in Coregen. Please check the "Reset Behavior" chapter in the FIFO Generator UG below (By the way, download Xilinx Document Navigator to manage all HW/SW/IP docs)
The FIFO starting 'Full' does look odd. Are there any warning messages? (I have never used ISIM, so I don't know exactly where they would appear).
Also, are you using the Structural simulation model for the FIFO?
07-19-2011 06:01 AM
07-19-2011 06:29 AM
I assume this is an asynchronous FIFO. If yes, the default reset value of the FULL flag is one. You can change the FULL reset value in Coregen.
Gosh! I really hadn't noticed that before. And in the XCO file for my latest Async FIFO, it says:
So, I probably just check the relevant box by instinct...