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Visitor cwiesner
Visitor
7,969 Views
Registered: ‎09-29-2015

Problems with the PLL of the Spartan-6, in particular the feedback path with a slow input clock.

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Hi,

 

I am implementing a DeSerializer of an LVDS Video Stream. I have some questions regarding the setup of the PLL_ADV. My design is based on XAPP1064, I am using an XC6SLX16.

 

The frequency of my input clock is 22MHz, the SERDES-Ratio is 7:1. I can not simply multiply the clock by 7, because this gets me 154MHz which is below the frequency range of the VCO (400-1080MHz). Instead, I multiply by 21. The resulting frequency from 462MHz is fine.

 

From this frequency I generate four frequencies:

- O1 is 462MHz / 1 which I only need for the feedback path

- O2 is 462MHz / 3 = 154MHz. This is my SERDES-Clock to drive the De-Serializer Logic

- O3 is 462MHz / 21, this is my input clock again

- O3 is 462MHz / 42, this is half the input clock

 

This works so far, but only with the setting "INTERNAL" of the PLL_ADV. I also use the CLKFBOUT-Output and route it back to CLKFBIN.

 

Now I want to implement the same feedback as in XAPP1064. They used the CLKOUT-Method, routed their signal via BUFPLL to the ILOGIC, did the SERDES and via BUFIO2 and BUFIO2FB back into the PLL for comparison.

 

This is not possible in my case, because my feedback signal is way to fast for SERDES. What do I do now? I could

  • Build a dummy feedback path without triggering anything
  • Route the 462MHz to my SERDES and implement a /3-divider somewhere
  • Use my official SERDES-Clock of 154MHz as feedback to the PLL. But how do I tell the PLL that her feedback is divided?

Thanks for any ideas.

 

kind regards,

Christian

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Instructor
Instructor
15,002 Views
Registered: ‎08-14-2007

Re: Problems with the PLL of the Spartan-6, in particular the feedback path with a slow input clock.

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In any case the output in the feedback loop does not need to run at the VCO frequency.  I believe M can be set to 1.  In your case you may want to set it to 7.  Then CLK0 would run at the bit rate.  You certainly don't need to make M 21.  Effectively the CLK0 divider times M wants to be 21 in order to get the correct VCO frequency so for example you can have a CLK0 output divider of 3 and a feedback divider of 7.  M only needs to be 21 if you select internal feedback.

-- Gabor
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Instructor
Instructor
7,949 Views
Registered: ‎08-14-2007

Re: Problems with the PLL of the Spartan-6, in particular the feedback path with a slow input clock.

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The feedback clock should have the same frequency as the input clock, not the VCO frequency.  So in your case the frequency should be 22 MHz.  The feedback clock and input clock go into a phase comparator within the PLL, so they should have the same frequency.

-- Gabor
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Visitor cwiesner
Visitor
7,945 Views
Registered: ‎09-29-2015

Re: Problems with the PLL of the Spartan-6, in particular the feedback path with a slow input clock.

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Hi Gabor,

 


@gszakacs wrote:

The feedback clock should have the same frequency as the input clock, not the VCO frequency.  So in your case the frequency should be 22 MHz.  The feedback clock and input clock go into a phase comparator within the PLL, so they should have the same frequency.


Thanks for your answer. But there is a divider, M, before the Phase Comparator (PFD). I have attached a picture from UG382.

 

If I want to generate a Clock O0 which is 10 times higher than CLKIN1 I would set M to 10. As a result, CLKFBIN is divided by 10. So, my PFD sees only every 10th pulse. He still can do his job of phase comparison, but he levels the voltage of the VCO so high that the VCO generates a clock 10 times CLKIN1. This is my understanding of the PLL.

 

Besides, the feedback-clock in XAPP1064 is multiplied as well.

 

kind regards,

ChristianUG832.png

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Instructor
Instructor
15,003 Views
Registered: ‎08-14-2007

Re: Problems with the PLL of the Spartan-6, in particular the feedback path with a slow input clock.

Jump to solution

In any case the output in the feedback loop does not need to run at the VCO frequency.  I believe M can be set to 1.  In your case you may want to set it to 7.  Then CLK0 would run at the bit rate.  You certainly don't need to make M 21.  Effectively the CLK0 divider times M wants to be 21 in order to get the correct VCO frequency so for example you can have a CLK0 output divider of 3 and a feedback divider of 7.  M only needs to be 21 if you select internal feedback.

-- Gabor
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Visitor cwiesner
Visitor
7,932 Views
Registered: ‎09-29-2015

Re: Problems with the PLL of the Spartan-6, in particular the feedback path with a slow input clock.

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Hi Gabor,

 

I think I got it. I have now set

CLKFBOUT_MUL   <= 7;

CLKOUT0_DIVIDE <= 3;

 

The feedback is CLKOUT0. It works, which means for me, that MAP does not generate any timing issues any more.

 

Thanks.

 

Christian

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Contributor
Contributor
6,627 Views
Registered: ‎12-07-2010

Re: Problems with the PLL of the Spartan-6, in particular the feedback path with a slow input clock.

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Hi Christian, Gabor,

 

I found your thread very useful as I am implementing a 7:1 cameralink with a 40Mhz source sync clock and am trying to use the XAPP1064 as a guide. Your last response confused me regarding setting the PLL's CLOCKOUT0_DIVIDE to 3....

 

I've been using UG382 Figure 3-5 PLL Using CLOCKOUT0 Feedback for my model of what's going on in XAPP1064. I'll paste it below but replace the I/O Input block with what I believe is happening with the ISEREDES2 block:

 

7to1serdes.jpg

 

Now as I understand it, I need to set:

CLKFEOUT_MULT = 7

CLKOUT0_DIVIDE = 1

DIVCLK_DIVIDE = 1

which means my input clock (clkin) gets multiplied by 7 so that the PLL output clock matches the bitstream (I call it clkin_x7). This is the main clock for the ISEREDES2 block and is then routed to CFB0. The M=7 then divides that clock down so that both clocks are x1 when entering the PLL's VCO. Unfortunately, 40Mhz x 7 x 1 / 1 = 280Mhz which falls short of the VCO's 400-1050Mhz frequency range. It seems like 40Mhz is too slow, but you seem to have been able to use 22Mhz. Am I implementing the clock incorrectly?

 

Any help would be greatly appreciated!

Thanks,

Peter

 

I'll also include how I've set up the PLL:

rx_pll_inst : PLL_BASE generic map(
          BANDWIDTH            => "OPTIMIZED",
          CLKFBOUT_MULT        => 7,
          CLKFBOUT_PHASE        => 0.0,
          CLKIN_PERIOD        => 25.0,
          CLKOUT0_DIVIDE        => 1,
          CLKOUT0_DUTY_CYCLE    => 0.5,
          CLKOUT0_PHASE        => 0.0,
          CLKOUT2_DIVIDE        => 7,
          CLKOUT2_DUTY_CYCLE    => 0.5,
          CLKOUT2_PHASE        => 0.0,
        COMPENSATION        => "SOURCE_SYNCHRONOUS",
          DIVCLK_DIVIDE        => 1,
        CLK_FEEDBACK        => "CLKOUT0",
          REF_JITTER        => 0.100)
    port map (
          CLKOUT0            => clkin_x7_pll_int,
          CLKOUT2            => clkin_pll_int,
          LOCKED            => clkin_lckd_int,
          CLKFBIN            => clkin_x7__iserdes_fb_buf,
          CLKIN            => clkin_iserdes_buf,
          RST            => reset) ;

 

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Observer bgaughan1
Observer
3,038 Views
Registered: ‎12-01-2009

Re: Problems with the PLL of the Spartan-6, in particular the feedback path with a slow input clock.

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Hopefully you resolved this. I had to something similar back in 2012 using M=14 and D=2 for a 54MHz flat panel display link to get above the 400MHz lower limit.

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