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Visitor novaelf
Visitor
6,397 Views
Registered: ‎07-28-2009

Programmng the sp601

Hi, I'm just got a sp601 board and to begin with, I'm still not very familiar with fpgas yet so bear with me.

 

I'm trying to learn how to

1. program the board with my own bitstream

2.send and receive my own data from the fpga, using software if possible.

 

The base reference design provides the HDL code; it uses ICAP_SPARTAN6 to program the fpga if I'm not wrong. I want to study the code to learn how to program it with ICAP_SPARTAN6, but it seems that the data comes in ethernet packets. I'm not familiar with ethernet packets and no source code is provided for the windows-application side, only the executable, so I'm not sure how I'm able to modify it to send my own data.  Are there other methods of programming bitstreams?

 

Then I checked for an alternative way to send data without using the ethernet. The standalone application examples seems to use EDK to program the fpga and send data with the USB JTAG. However, the sp601 board isn't supported in the EDK yet.

 

Can anyone give me advice on how to proceed with this?

Thanks.

 

Ben

Message Edited by novaelf on 11-26-2009 12:54 AM
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6 Replies
Visitor novaelf
Visitor
6,384 Views
Registered: ‎07-28-2009

Re: Programmng the sp601

Just to add on, I hope to program it in a generic way that does not rely on xilinx tools. I am not sure if this is possible.
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Xilinx Employee
Xilinx Employee
6,364 Views
Registered: ‎01-03-2008

Re: Programmng the sp601

A couple of very important things that you need to come up to speed on.

 

1) You don't program a board, you design a FPGA and load a bitstream.  In the case of the SP601 you will be design for a Spartan-6 LX16 (XC6SLX16CS324-2)

2) The ICAP block is an internal block that enables partial reconfiguration from the FPGA fabric.  Partial reconfiguration is a very advanced design methodology and as a new user you should not consider this.

3) Loading a bitstream is usually done through JTAG not Ethernet either by directly loading it into the FPGA or storing it a PROM or FLASH device.  The SP601 includes an embedded USB-to-JTAG controller.

4) The only way to design an FPGA is using Xilinx designs

 

I think that the SP601 will be supported in EDK 11.4 release to enable MicroBlaze designs.  If you are not creating a MicroBlaze design you will not be using EDK and will just use the ISE tools.

------Have you tried typing your question into Google? If not you should before posting.
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Visitor novaelf
Visitor
6,340 Views
Registered: ‎07-28-2009

Re: Programmng the sp601

The ug518 manual states that xilinx IMPACT tools are used to load the bitstream using the bitstream using the USB-to-JTAG port.

Are there any libraries that can be used to control the loading using written c applications instead of xilinx gui?

 

Ben

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Xilinx Employee
Xilinx Employee
6,330 Views
Registered: ‎01-03-2008

Re: Programmng the sp601

Impact can be run in a batch mode.
------Have you tried typing your question into Google? If not you should before posting.
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Observer xiaochh
Observer
6,302 Views
Registered: ‎05-06-2008

Re: Programmng the sp601

" I think that the SP601 will be supported in EDK 11.4 release to enable MicroBlaze designs " ----what's that mean..? It is to say in EDK11.3, we can't download the designs with SP601 ?!
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Xilinx Employee
Xilinx Employee
6,291 Views
Registered: ‎01-03-2008

Re: Programmng the sp601

EDK is a design tool for Processor Designs and it uses the ISE tools to actually implement and configure the device.

 

EDK 11.4 will have full support creating processer designs for the Spartan-6 devices.

 

ISE 11.2 and higher have full support for creating Spartan-6 designs and configuring devices.

------Have you tried typing your question into Google? If not you should before posting.
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