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Observer ikalogic
Observer
636 Views
Registered: ‎08-23-2011

Question about constraining DDR source synchronous deserialization

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Hi,

 

So here is the situation: I am reading the xapp1064, and downloaded the example designs. 

 

I've looked at all relevant example *VHD files and corresponding *UCF files.

 

On thing struck me: in the UCF, I only see one timing constrain:

 

# Timing

net "rx_bufg_x1" 	period = 125 MHz ; # Receiver global buffer = bit rate/serdes factor eg 1 Gbps/8

Ok, I know: Xilinx tool will automatically calculate the relevant constraints on other inputs. It this particular example the input LVDS clock is 500MHz DDR. (or 1Gbps). So that's fine, my most imporant question is: I see no where a constraint that constrains the input data to the input clock. Is it not needed? 

 

 

In other words, isn't something like this needed? 

 

 

TIMEGRP "INPUT_TIME_GROUP" OFFSET = IN 0.5 ns VALID 1 ns BEFORE "DCK_P" RISING;
TIMEGRP "INPUT_TIME_GROUP" OFFSET = IN 0.5 ns VALID 1 ns BEFORE "DCK_P" FALLING;

In the example above, DCK_P/_N is the input 500MHz DDR LVDS clock.

 

 

Actually, that constrain is almost impossible to be met, and PAR will almost always fail to satisfy this constraint. So I am starting to think that one does not need to specify this constrain, is that correct?

 

Thank you very much!

 

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Historian
Historian
698 Views
Registered: ‎01-23-2009

Re: Question about constraining DDR source synchronous deserialization

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(I know that you already saw this posting, but for everyone else...)

 

Take a look at this post about constraining dynamically calibrated interfaces.

 

The referenced post is for Vivado. For ISE, it is even simpler - simply don't put any OFFSET IN constraints on the input pins...

 

Avrum

2 Replies
Historian
Historian
699 Views
Registered: ‎01-23-2009

Re: Question about constraining DDR source synchronous deserialization

Jump to solution

(I know that you already saw this posting, but for everyone else...)

 

Take a look at this post about constraining dynamically calibrated interfaces.

 

The referenced post is for Vivado. For ISE, it is even simpler - simply don't put any OFFSET IN constraints on the input pins...

 

Avrum

Observer ikalogic
Observer
578 Views
Registered: ‎08-23-2011

Re: Question about constraining DDR source synchronous deserialization

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Thanks!

 

I know it was obvious, but I just needed a confirmation, and you gave me just that!

 

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