UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie weber1030
Newbie
3,233 Views
Registered: ‎06-21-2011

Questions about FIFO GENERATOR V6.2

Jump to solution

Hello everyone ,I am a learner of FPGA,I met a problem these days.

 

Under ISE 12.3,I generated a FIFO with FIFO GENERATOR v6.2.Here are the properties

 

Page1: Independent Clocks (RD_CLK, WR_CLK), Block RAM


Page2: Standard FIFO 

 

              Write Width: 16

 

              Write Depth: 256

 

              Read Width : 16

 

              Read Depth : 256


Page3: No item is selected


Page4: Reset Pin is not selected,default for other items


Page5: Default


Page6: Default


In the top .vhd file signal wr_clk is 500K Hz ,rd_clk is 5M Hz.

 

I want to realize a function by controlling wr_en and rd_en.when an external signal is enabled,write FIFO begins,when signal full is pulled up, write stops and at the same time read FIFO begins.After synthesizing,I made a simulation in MODELSIM.Here comes the problem.when writing process is done,wr_en is pulled down to '0' and reading begins according to 50M Hz,but after several data have been read out,signal full is still '1','1' lasts for 5 wr_clk clocks.

 

PS:I did another test under ISE 9.1(FIFO ) with the same codes,only to find that '1' of full only lasts for one wr_en clock.

Here I provide the .VHD file,some notes have been made.You can create a project and do a  simulation to preferably understand what I have said。Appreciates!!!

0 Kudos
1 Solution

Accepted Solutions
Teacher rcingham
Teacher
4,241 Views
Registered: ‎09-09-2010

Re: Questions about FIFO GENERATOR V6.2

Jump to solution
For dual clock FIFOs like this, there have been problems with the behavioural simulation models, so I advise you to use the structural simulation model.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

View solution in original post

0 Kudos
2 Replies
Teacher rcingham
Teacher
4,242 Views
Registered: ‎09-09-2010

Re: Questions about FIFO GENERATOR V6.2

Jump to solution
For dual clock FIFOs like this, there have been problems with the behavioural simulation models, so I advise you to use the structural simulation model.

------------------------------------------
"If it don't work in simulation, it won't work on the board."

View solution in original post

0 Kudos
Visitor hafblud
Visitor
3,125 Views
Registered: ‎01-25-2012

Questions about FIFO GENERATOR V6.2

Jump to solution

Hi

I am also having problem using the FIFO V6.2

I configured the FIFO (XILINX 12.2) as following (spartan3E)

  1. Independent Clock

  2. Block RAM

  3. FIFO width (R/W) = 8 bit

  4. FIFO depth (R/W)= 2048

 

The problem is when I write the FIFO, I cannot write above 410 bytes. The FIFO width is 2048 but it only writes 410 bytes. Why is so?

I am using 11.0592MHz Clock for writing the FIFO.

The second problem is that when I am wriring, I need to keep the wrEnable signal asserted for 5 wrClocks in order to write a single byte, this also i don't understand. Any help or guidance will be appreciated ?

 

regards

Ali

Tags (2)
0 Kudos