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Observer rty
Observer
8,267 Views
Registered: ‎10-08-2010

Questions about Spartan-6 GTP and BRAM

Hello.

 

I began to read documentation on Spartan-6 and have two questions about this ICs.

 

1. Are GTPs of Spartan-6 compatible to SONET OC-12 (maybe OC-48 or OC-3 with oversampling) or SDH STM-4 (STM-16, or STM-1 with oversampling)? As I read, all parameters in datasheet are good, but there are no OC-x (STM-x) templates in GTP configuration wizard for ISE (as opposed to Virtex-5) and nowhere written that these interfaces are compatible with S6 GTPs.

So please say, do anybody tested Spartan-6 GTPs with these interfaces? (for example, on SP605 board with proper SFP)

 

2. In a document "Spartan-6 FPGA Block RAM Resources User Guide(v1.2)", chapter "Conflict Avoidance" is written the next text:

 

In READ_FIRST mode only, the dual-port block RAM has the additional restriction
that addresses for port A and B cannot collide.


So we can think that in WRITE_FIRST mode there is no restriction on Address overlap.

 

But if we will read AR# 34533 ( http://www.xilinx.com/support/answers/34533.htm ),

there is the next text:

Behavior in Software:

  • ISE 12.3 (available in early Oct) and later - the software has been updated to include SDP Write First Mode as the preferred workaround to the Address Overlap issue.  In SDP Write First Mode, address overlap may occur, but it would only result in a failed read, and not a corruption of the memory cell(s).

So we can think that in WRITE_FIRST mode this issue also exists, but influence only on result of reading, not writing.

 

So, I have questions:

1) Is there an Address overlap problem in SDP Write First Mode (as said in AR# 34533 and not said in Spartan-6 FPGA Block RAM Resources User Guide).

2) Is there an Address overlap problem in TDP modes of BRAM?

 

So, is it possible to use Spartan-6 BRAM in some particular of dual port modes without thinking about address overlap problems?

 

Thank you in advance for answers and excuse me for bad English.

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17 Replies
Observer rty
Observer
8,224 Views
Registered: ‎10-08-2010

Re: Questions about Spartan-6 GTP and BRAM

Anybody help...

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Moderator
Moderator
8,207 Views
Registered: ‎05-17-2010

Re: Questions about Spartan-6 GTP and BRAM

I can address your BRAM question.  First of all, when we're referring to the Address Overlap, or Collision, issue in the S6 and V6 BRAMs, we are specifically referring to an issue that results in the corruption of the BRAM address space when address overlap occurs.

 

The other point which should not be looked at in the same category is present on all RAMs in general.  The User Guide does address this point, however you may not have recognized that it was made.  In the bullet point above the one you reference in UG383, it is stated that:

 

When one port performs a write operation, the other port must not read- or writeaccess
the same memory location. The simulation model will produce an error if this
condition is violated. If this restriction is ignored, a read or write operation will
produce unpredictable results. There is, however, no risk of physical damage to the
device. If a read and write operation is performed, then the write will store valid data
at the write location.

 

1) So, if you are in SDP Write First mode and your addresses overlap while using asynchronous clocking, your write will succeed but your read may not result in the correct results.  It is not, however, the same as the address overlap issue because the memory contents are not corrupted.

 

2) The issue only occurs when using Read First mode with either of the following setups with different clocks clocking CLKA and CLKB of the Block RAM:

  • True Dual Port (TDP) mode with WRITE_MODE = READ_FIRST for the RAMB16BWER or RAMB8BWER components
  • Simple Dual Port (SDP) mode with WRITE_MODE = READ_FIRST for the RAMB8BWER component

I hope that clarifies it.  Reply to the post if you have any further questions.

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Observer rty
Observer
8,195 Views
Registered: ‎10-08-2010

Re: Questions about Spartan-6 GTP and BRAM

Hello.

 

Thank you for answer.

 

So, if I will configure all BRAMs in True Dual Port (TDP) mode with WRITE_MODE = WRITE_FIRST, I will not have Address overlap problem? (as described here: http://www.xilinx.com/support/answers/34533.htm in Table 1)

 

I need some FIFOs with independent clocks on input and output.

Will I have Address overlap problem, if I make a FIFO core by FIFO core generator?

As I understand, such FIFO will be created in Spartan-6 by FIFO generator with using BRAM Block(s).

Will this FIFO work good, or it must be specially designed/configured for avoiding address overlap problem in a FIFO core?

 

Thank you in advance.

 

 

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Moderator
Moderator
8,186 Views
Registered: ‎05-17-2010

Re: Questions about Spartan-6 GTP and BRAM

TDP in Write First mode will not have the address overlap/collision issue as described in that AR.  The FIFO Generator from Xilinx will design your FIFOs to avoid the issue if you target 12.2 or later.  If you are able to use 12.3, that would be preferred.

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Observer rty
Observer
8,165 Views
Registered: ‎10-08-2010

Re: Questions about Spartan-6 GTP and BRAM

Thank you for answer!

 

And what about Spartan-6' GTPs to SONET/SDH compartibility?

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Observer mit_brooks
Observer
8,119 Views
Registered: ‎01-29-2008

Re: Questions about Spartan-6 GTP and BRAM

We are designing a board for a Sonet/SDH application.

Although there are no templates, the gtp user guide (UG386) does mention Sonet and SDH in it, so it can't be incompatible.

We have an SP605 board with a finisar FTLF1322P1xTR SFP module and have sucessfully done a loopback test on it using chipscope.

I think the biggest problem would be the reference clock design. We are using DS3106 as the reference clock source, feeding it a recovered clock from the GTP for synchronisation.

 

You mentioned OC-3 using oversampling. We would like to do that too. Have you found any docs about how to do this in S6? XAPP875 would be great if it could be ported to S6. Have you  tried that? I've only come accross it today so haven't had a chance to try... documentation says its for V5 and demo code will have to be converted for S6 - if its possible... there s an .NGC file in it...

Tim

 

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Observer rty
Observer
8,103 Views
Registered: ‎10-08-2010

Re: Questions about Spartan-6 GTP and BRAM

Hello.

Thank you for answer.

 

I didn't tryed Spartan-6, now I am waiting for SP605 Board for testing it.

 

>You mentioned OC-3 using oversampling. We would like to do that too. Have you found any docs about how to do this in S6?

 

No, I didn't. I only read "Spartan-6 GTP user guide" and compared it with "Virtex-5 GTP user guide" where hardware for oversampling is present.

I will try to make this by working on 622 Mhz and sending and receiving every bit 4 times.

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Visitor alleninf
Visitor
7,534 Views
Registered: ‎05-05-2011

Re: Questions about Spartan-6 GTP and BRAM

Hi,

 

Have you been able to test OC-3 over Spartan-6? What is your result?

 

I'm also trying to implement OC-3 on Sp-6 GTP. What I have done is making PMA loopback working but not PCS loopback on SP605 board. Any hint?

 

Thanks!

Tags (1)
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Observer rty
Observer
7,503 Views
Registered: ‎10-08-2010

Re: Questions about Spartan-6 GTP and BRAM

Hello.

 

I've tested STM-1 on SP605.

I didn't tryed loopbacks, frames are disassembled and assembled in logic.

 

I've tuned GTP for 622.08 MHz and received and transmitted every bit 4 times.

It works.

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Visitor alleninf
Visitor
7,482 Views
Registered: ‎05-05-2011

Re: Questions about Spartan-6 GTP and BRAM

Hi, Rty:

 

Thanks for your answer. But I have below question:

1, What is your ref clock speed? How do you get 622Mhz?

2, How do you do 4 times oversampling?

3, I assume that you create the function by using CoreGen, right? Could you share your coregen project?

 

Thanks!

 

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Observer rty
Observer
7,469 Views
Registered: ‎10-08-2010

Re: Questions about Spartan-6 GTP and BRAM

Hello.

 

1. 155.52 Mhz

2-3. Oversampling is a process in my Verilog code.

On RX side, bits "11110000" coming at the speed 77.76 are converted to bits "10" with rate 19.44 .

On TX side, bits "01" coming at the speed (in logic) 77.76 are converted to bits "00001111" with rate 77.76.

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Visitor alleninf
Visitor
7,460 Views
Registered: ‎05-05-2011

Re: Questions about Spartan-6 GTP and BRAM

Hi,

 

Ok, I got that you implement oversampling in your Verilog code.

 

Have you done any jitter test? I'm not worry about Tx side. But, on Rx side, do you meet OC-3 jitter tolerance spec?

 

Thanks!

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Observer rty
Observer
7,452 Views
Registered: ‎10-08-2010

Re: Questions about Spartan-6 GTP and BRAM

You can find an answer to your question even with the pictures if you make a search to this forum by my nickname :).

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Highlighted
Observer armando
Observer
7,257 Views
Registered: ‎05-28-2011

Re: Questions about Spartan-6 GTP and BRAM

Hi Rty,

I am a new user and  want to transmit/receive OC-12 SONET/SDH   Data by Spartan-6' GTPs . and no in ISE GTP configuration wizard any template . could  you please give me your .ucf file or any help to use it .

Thank you very much.

armando.

Tags (1)
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Historian
Historian
7,251 Views
Registered: ‎02-25-2008

Re: Questions about Spartan-6 GTP and BRAM


@armando wrote:

Hi Rty,

I am a new user and  want to transmit/receive OC-12 SONET/SDH   Data by Spartan-6' GTPs . and no in ISE GTP configuration wizard any template . could  you please give me your .ucf file or any help to use it .

Thank you very much.

armando.


If you are a new user, why are you trying to do one of the more difficult jobs for an FPGA, rather than something simple, like blinking LEDs and reading switches?

----------------------------Yes, I do this for a living.
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Observer armando
Observer
7,246 Views
Registered: ‎05-28-2011

Re: Questions about Spartan-6 GTP and BRAM

Hi,

Oh sorry for my question,

but I am a new user by spartan not by fpga.

I am working by Virtex 5 and want to go to spartan6.

thank you and excuse me.

 

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Visitor zeshan13
Visitor
7,237 Views
Registered: ‎07-27-2012

Re: Questions about Spartan-6 GTP and BRAM

Dear mit_brooks!
Have you tested your OC3 design with live data stream?
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