I was wondering if anyone on here has any advice on the following problem:
I have a requirement to connect two seperate 1x PCIe lanes to a XC6SLX45T FPGA. These two lanes will never be used at the same time and the FPGA will be reconfigured depending on the build option to change the PCIe pins used.
I was thinking of connecting the one lane to the default PCIe endpoint pinouts, as is done for the SP605 development board, and the other lane to the 2nd transceiver of the same tile.
For the first build option in my design, the FPGA will then be configured to use the default pins and for the second build option the FPGA will be configured to use the alternate pins.
1) If I do this, will I need to route a second sys_clk differential pair to the 2nd transceiver clock inputs or can I use the first tranceiver's clock inputs as the reference source for the 2nd transceiver?
2) Keeping both lanes on a single tile will allow me to leave the second GTP tile unpowered and while efficiency is important to me, having a working PCIe setup is more crucial. Would it be safer to move the second PCIe lane to a different tile or should my proposed solution be fine?