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stmartin81
Adventurer
Adventurer
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Registered: ‎12-09-2010

Reducing clock jitter for output clocks on Spartan 3E and Spartan 6 devices

Hello,

 

I'm currently working on a project which uses a Spartan 3E FPGA which is going to be replaced by a Spartan 6 FPGA. I have an external clock input signal which should get shifted by a variable phase. For this I'm using the DCM. Is it recommended to use a PLL after the DCM on the Spartan 6 device if I want to achieve the lowest possible clock jitter? The Spartan 3E device doesn't seem to have a PLL.

 

 

Best regards

Martin

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austin
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Registered: ‎02-27-2008

Martin,


How low, do you need to go?  Any clock, once it is inside the FPGA, will have roughly 100 ps peak to peak jitter imposed on it from all the internal switching that is going on, in the best case.  If you have poor bypassing (decoupling), and poor signal integrity, that number can easily reach 1000 ps.  No PLL will make any of this better, as it is in the same fabric as the rest.

 

Given that you wish to remove the tap jitter from a DCM, a PLL is good for that, but we are talking about 30-50 ps, which is down in the noise (literally).


If the clock coming in has a lot of jitter, and there is nothing you can do to improve it, then yes, use the PLL to make it better.


The pole for the phase detector filter for the PLL is about 300 KHz for the long time contant, and about 1 MHz for the short time constant, so no jitter with frequencies below those numbers will be filtered.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
stmartin81
Adventurer
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Registered: ‎12-09-2010

Hi Austin,

 

I don't have a requirement on how low the jitter has to be. I'm just trying to get an overview on the options I have as this is my first project where I have to deal with phase shifting and jitter. The input clock has a frequency of 13.5 MHz and I need to be able to shift the clock in the FPGA by 360° with a granularity of 2°.

 

I think it was in the Spartan 6 datasheet where I've read that it is recommended to use a PLL after a DCM to reduce clock jitter. It was also mentioned that it is possible to add a PLL before a DCM if one wanted to use the PLL output clock in several DCMs. 

 

 

Best regards

Martin 

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austin
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Registered: ‎02-27-2008

Martin,

 

If you don't need it, don't use it.

 

If you don't know what the requirement is, there probably isn't any.

 

Some applications that are sensitive to jitter:  A/D and D/A conversion clocks (reduce the effective number of bits resolution when jitter is out of that specified), high speed DDR source synchronous interfaces (above ~250-300 MHz, 500-600 Mb/s).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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