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Participant
9,085 Views
Registered: ‎08-17-2011

## Regarding the Pulse generation in vhdl

Hi,

Can anyone Please let me know how to generate 3.3 usec clock from  62.5 nsec base oscillator clock.? Please do let me know.

Thanks,

V. Prakash

59 Replies
Teacher
8,933 Views
Registered: ‎09-09-2010

Ratio is 52.8 = 264/5.
A probably good enough way to do it is a x5 DCM followed by a divide-by-264 (which is an even number, so if you really need a clock, rather than a clock enable, you can even get 50 mark/space ratio).
The intermediate 80MHz clock should work ok.

What Spartan are you using?
Where does the clock go?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
Participant
8,926 Views
Registered: ‎08-17-2011

Hi,

1) I am using Spartan 3AN (XC3S50AN)

2)  This 3.3 usec clock generated is given to the clock of BRAM

My Base clock oscillator for FPGA is 16.6 mhz

Can you please explain this in details.

Ratio is 52.8 = 264/5. ?

Thanks,

V. Prakash

Teacher
8,921 Views
Registered: ‎09-09-2010

Your original post stated that the oscillator period is 62.5ns, which is 16MHz. Is it that, or is it 16.6MHz? Or is it 16.666667MHz?

And what it the exact BRAM operating frequency/period?

The exact frequencies are very important.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
Participant
8,899 Views
Registered: ‎08-17-2011

Hi,

The Exact operating frequency of Bram is 3.3 usec(OFF time= 1.65 usec and ON time= 1.65 usec).

The Base Oscillator frequency is 16.6 Mhz. Please let me know how to generate this 3.3 usec from the base oscillator of

16.6 Mhz

Thanks,

V. Prakash

Professor
8,897 Views
Registered: ‎07-21-2009

Sounds like you need to multiply the 16.6MHz input clock by 2, and then in the fabric divide the 33.2MHz clock by 110.  The result should be a 3.313253 uS period square wave, which you can buffer (with a BUFG) for use as a clock.

A 'perfect' 16.6666666 MHz input clock multiplied by 2 and then divided by 110 would result in a 3.3uS period square wave.

-- Bob Elkind

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8,895 Views
Registered: ‎10-05-2010

Is there any particular reason why you want to run the BRAM at 303 kHz? You might be able to get away with using a higher integer multiple of the clock speed, and then just use a slow clock enable (at 303 kHz) for the read and write operations.

Without knowing exactly what your ultimate goal is, this is just speculation, of course.

Participant
8,882 Views
Registered: ‎08-17-2011

Hi,

Please refer the attachement. I have to generate these dval and lval pulses. For this, i had asked 3.3 usec from my 16.6Mhz.

Thanks,

V. Prakash

8,880 Views
Registered: ‎10-05-2010

Is the "BRAM" the FPGA's internal memory, or some external chip?

Participant
8,878 Views
Registered: ‎08-17-2011

Hi,

The BRAM  is the Block ram inside the FPGA only. Not an external RAM.

Thanks,

V. Prakash

Teacher
9,069 Views
Registered: ‎09-09-2010

So, now that we have established that want you want are some strobes produced by cascading counters, we return to the question of what your system clock is: 16.6MHz (60.24096... ns period) or 16.666667MHz (60 ns period).

There is an additional question of the permitted tolerance on the 3.3 us period strobe.

The LVAL strobe is high for 256 DVAL periods, and low for 44, so that is almost trivial, with a divide-by-300 counter, using the MSB. Does LVAL start at 0 or 1?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
Participant
9,061 Views
Registered: ‎08-17-2011

Hi,

The system clock is: 16.6MHz (60.24096... ns period)

Lval starts at rising edge (1). During Lval rise, Dval should fall.( refer the image attached for this)

how to generate these pulses. Please explain in details.

thanks,

V. Prakash

Participant
9,045 Views
Registered: ‎08-17-2011

Hi Experts,

Can you give some idea on this pulse generation. Please help on this.

Thanks,

V. Prakash

Professor
9,034 Views
Registered: ‎07-21-2009

The term "clock" has a special meaning in the context of FPGA design.  It's now quite clear that you do not need to generate a clock for internal use in the FPGA, and this misunderstanding wasted some time and effort trying to help you.  It is apparent from your post #8 in this thread that you have a data interface to design.

It would help to know the following:

• the use and meaning of the D, DVAL, and LVAL signals
• the timing requirements, including tolerances, of these signals
• the source of the D, DVAL, and LVAL signals

Can you provide these details?

If the timing requirements are loose enough, you can generate the needed signal timing from the 16.6MHz clock with simple dividers and state machines.

If the timing requirements are too tight to be derived conveniently from the 16.6MHz clock, you may be forced to choose a master clock frequency which is locked to a multiple of the desired D rate.

-- Bob Elkind

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Participant
9,023 Views
Registered: ‎08-17-2011

Hi,

LVal =>(On time = 844.8 usec and Off time = 145.2 usec) continuously and Dval =>(On time = 3.3 usec and Off time =3.3usec ) continuously. These two pulses will be given to the External controller from FPGA.
For every falling edge of Dval, the one 8 bit data will be be send from the external controller to the FPGA and kept in FPGA RAM. The FPGA have to receive that data in the raising edge of that clock. DVAL and Clock to the RAM are the same. So, for every falling edge, one data will be send from External controller to FPGA and for every raising edge, that data will be received in the FPGA For 3.3 usec, one data. So for 844.8 usec, 256 datas will be received from controller to FPGA RAM.

6 RAMs in one FPGA will receive data from 6 different controllers parallely. Controllers and FPGA are synchronised with the clock of 3.3usec as i mentioned above.
For 256 Clocks, each clock = 3.3usec, the 6 RAMS of 256x8 will be filled from external controller. I have to send these datas in the order of RAM1 datas first, then RAM2, RAM3,RAM4, RAM5 and RAM6(totally 1536 datas) using the Multiplexer.

Multiplexer Select line --> 000 = RAM1 (256 Datas)
001 = RAM2 (256 Datas)
010 = RAM3 (256 Datas)
100 = RAM4 (256 Datas)
101 = RAM5 (256 Datas)
110 = RAM6 (256 Datas)

This LVAL and Dval pulse is to synchronize the External controller. in that  pulse diagram, there is no need for D pulse.

I have to generate Lval and Dval pulse only in it. i have to generate these pulse accurately.

Thanks,

V. Prakash

9,020 Views
Registered: ‎10-05-2010

Generating these timed pulses is pretty straightforward to do with a state machine.

You'll need to decide how precise you want the timing to be. Let's assume that a period of 1.66 usec is an acceptable approximation of your 1.65 usec half-period. This will be 1/100 of the 16.6 MHz clock.

Now you can make a clock enable that triggers every 100 cycles (1.65 usec)

```reg [6:0] counter = 0;
wire enable1u66;

always @(posedge clk16M6)
if (counter == 99)
counter <= 0;
else
counter <= counter + 1'b1;

// Assert the clock enable every 100 cycles
assign enable1u66 = (counter == 7'd0);
```

Your LVAL and DVAL signals are essentially independent of each other, so you can deal with them separately.

DVAL:

```reg dval = 0;

always @(posedge clk16M6)
if (enable1u66)
dval = ~dval;
```

LVAL:

```reg lval = 0;
reg lvalstate = 0;
reg [9:0] lvalcount = 0;

always @(posedge clk16M6)
if (enable1u66)
case(lvalstate) begin
0: begin
// Keep LVAL high for 512 cycles
lval <= 1;

if (lvalcount == 511) begin
lvalstate <= 1;
lvalcount <= 0;
end else
lvalcount <= lvalcount + 1'b1;

end

1: begin
// Keep LVAL low for 88 cycles
lval <= 0;

if (lvalcount == 87) begin
lvalstate <= 0;
lvalcount <= 0;
end else
lvalcount <= lvalcount + 1'b1;

end

end```

Disclaimer: wrote this off the top of my head, so it has not been tested. I take no responsibility for destroying your external controller with off-by-one errors in the counting logic, or any other sort of error.

Hopefully this will give you enough insight into how these sorts of signals can be generated in an FPGA. We'll leave the multiplexer logic up to you!

Tags (1)
Professor
9,005 Views
Registered: ‎07-21-2009

Let's assume that a period of 1.66 usec is an acceptable approximation of your 1.65 usec half-period. This will be 1/100 of the 16.6 MHz clock.

Ooops...  16.6MHz divided by 100(d) is 0.166MHz (or 166KHz), not 1.66 uS.

Starting over --

• 16.6MHz clock has a period of roughly 60.24 nS
• Desired DVAL output clock period is 3.3 uS, or 3300.00 nS
• Dividing 3300.00 by 60.24 yields (rounded to the nearest integer) 55.

So the nearest we can easily arrive at 3.3 uS pulse from 16.6MHz is approximately 301.82 KHz, or 3.31325 uS

If this is an acceptable deviation (+ 0.4%) from the nominal 3.30 uS target, we can proceed.

Starting with joelby's code, let's make a few changes...

```reg [6:0] counter = 0;reg dval = 1;  // dval output to external video data sources, roughly 301.82KHz (3.31325uS)wire enable1u66;  // pixel-rate, single-cycle clock enable pulsealways @(posedge clk16M6) // generate single-cycle pixel-rate clock enable pulse  if (counter >= 54) // divide 16.6MHz by 55    counter <= 0;  else
counter <= counter + 1'b1;// Assert the clock enable every 55 cycles, a pixel-rate pulse// enable1u66 clock enable pulse coincides with last clock cycle before dval 1=>0 transitionassign enable1u66 = (counter == 7'd28);always @(posedge clk16M6)  dval <= (counter < 7'd28);  // dval has 28/27 duty cycle```

LVAL:

```reg lval = 0; // output to external video data sources -- ON for 256 pixels periods, OFF for 44 pixel periods
reg lvalstate = 0;
reg [7:0] lvalcount = 0;

always @(posedge clk16M6)
if (enable1u66)  // advance at pixel rate, output changes are coincident with dval falling edge
case(lvalstate)      0:    // Keep LVAL low for 44 cycles       if (lvalcount == 43) begin   // LOW period is over          lvalstate <= 1;          lval      <= 1;          lvalcount <= 0;  // reset the counter        end else          lvalcount <= lvalcount + 1'b1;      1:    // Keep LVAL high for 256 cycles
if (lvalcount == 255) begin  // HIGH period is over
lvalstate <= 0;          lval      <= 0;          lvalcount <= 0;  // reset the counter
end else
lvalcount <= lvalcount + 1'b1;
endcase```

-- Bob Elkind

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8,988 Views
Registered: ‎10-05-2010

Thanks for the corrections, Bob! I knew that my calculations were a bit fishy and should have simulated/tested it, but it was getting late.

Participant
8,982 Views
Registered: ‎08-17-2011

Hi Experts,

Thanks for your code and valuable reply. But I dont know about verilog. I am using VHDL for my coding. Can you Please translate this into VHDL. This will be helpful to me and also i will be thankful to you experts. Please help.

Thanks,

V. Prakash

Professor
8,978 Views
Registered: ‎07-21-2009

I am sure that my proficiency for writing VHDL code is much worse than your proficiency for reading Verilog.  :)

-- Bob Elkind

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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Participant
8,300 Views
Registered: ‎08-17-2011

Hi Experts,

Is there any converter software from verilog to vhdl? Can anyone translate the above verilog  code into vhdl? Please help.

Thanks,

V. Prakash

8,299 Views
Registered: ‎10-05-2010

It's incredibly simple code - if you know any VHDL it should only take you a minute or two to translate it.

Change always @(posedge clk) to process (clk) begin .. if (rising_edge(clk)) .. that sort of thing (I don't know VHDL either, sorry)

If you're having trouble with basic VHDL constructs, you should seriously consider spending some more time working through the tutorials in your textbook before proceeding. The languages aren't so different, superficially, that it's difficult to infer the intent of simple code of one if you're versed in the other.

Professor
8,293 Views
Registered: ‎07-21-2009

Is there any converter software from verilog to vhdl? Can anyone translate the above verilog  code into vhdl?

This is an extraordinarily bad idea.

• No-one knows if this code actually works
• This code has not been written to work in your design
• Even if this code works without *ANY* changes, how will you know?
• Do you think you should write the entire rest of your design around 15 or 20 lines of untested code written by strangers?

Help yourself, first, by learning how to write your own code instead of copying code that you do not understand.

If you cannot understand the simple code which joelby has posted, your chances of successfully completing *any* design are nil.  So learn.  Find a textbook or an online tutorial, find some example 'starter' designs which are just a few gates or counters, and learn by experimenting and correcting your mistakes.

Here is a good 'starter' website: www.fpga4fun.com.

Good luck.

-- Bob Elkind

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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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Participant
8,276 Views
Registered: ‎08-17-2011

Hi experts,

I had changed the verilog code to vhdl code.

Base oscillator clock = 16.6 mhz = clk16M6
Dval Pulse--> On time = 1.66 usec and off time = 1.66 usec (3.32 usec) continuously
Lval Pulse--> On time = 849.92 usec and off time = 146.08 usec continuously

Below is the verilog code for the above pulse generation:

reg [6:0] counter = 0;
wire enable1u66; // pixel-rate, single-cycle clock enable pulse

always @(posedge clk16M6) // generate single-cycle pixel-rate clock enable pulse
if (counter >= 54) // divide 16.6MHz by 55
counter <= 0;
else
counter <= counter + 1'b1;

// Assert the clock enable every 55 cycles, a pixel-rate pulse
assign enable1u66 = (counter == 7'd0);

--DVAL:

reg dval = 1; // dval output to external video data sources, roughly 301.82KHz (3.31325uS)

always @(posedge clk16M6) dval <= (counter < 28); // dval has 28/27 duty cycle

--LVAL:

reg lval = 0; // output to external video data sources -- ON for 256 pixels periods, OFF for 44 pixel periods
reg lvalstate = 0;
reg [7:0] lvalcount = 0;

always @(posedge clk16M6)
if (enable1u66)
case(lvalstate)
0: // Keep LVAL low for 44 cycles
if (lvalcount == 43) begin // LOW period is over
lvalstate <= 1;
lval <= 1;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;

1: // Keep LVAL high for 256 cycles
if (lvalcount == 255) begin // HIGH period is over
lvalstate <= 0;
lval <= 0;
lvalcount <= 0; // reset the counter
end else
lvalcount <= lvalcount + 1'b1;

endcase

VHDL Code for the above verilog code is:

entity pulse_generation is
port ( clk16M6 : in std_logic;
dval: out std_logic;
lval: out std_logic := 0);
end pulse_generation;

architecture Behavioral of pulse_generation is

signal counter: unsigned(6 downto 0);
signal enable1u66: std_logic;
signal lvalstate: std_logic := '0';
signal lvalcount : std_logic_vector(7 downto 0) := "00000000";

begin

process(clk16M6)
begin
if rising_edge(clk16M6) then
enable1u66 <= '0';
if counter >= 54 then
counter <= "0000000"
enable1u66 <= '1';
else
counter <= counter + 1;
end if;
end if;
end process;

-- dval generation
process(clk16M6)
begin
if rising_edge(clk) then
if counter < 28 then
dval <= '1';
else
dval <= '0';
end if;
end if;
end process;

--lval generation
process(clk16M6)
if (enable1u66 = '1')
case(lvalstate)
0: -- Keep LVAL low for 44 cycles
if (lvalcount == 43) begin -- LOW period is over
lvalstate <= 1;
lval <= 1;
lvalcount <= "00000000"; -- reset the counter
end else
lvalcount <= lvalcount + 1;
end if;

1: -- Keep LVAL high for 256 cycles
if (lvalcount == 255) begin -- HIGH period is over
lvalstate <= 0;
lval <= 0;
lvalcount <= 0; -- reset the counter
end else
lvalcount <= lvalcount + 1;
end if;
end if;

endcase;

end behavioural;
can you please check the vhdl code for lval generation is correct.?
8,274 Views
Registered: ‎10-05-2010

Kudos to the kind folk at the edaboard.com forum! ;)

Have you simulated the code? Does it produce the desired result?

Professor
8,272 Views
Registered: ‎07-21-2009

Kudos to the kind folk at the edaboard.com forum!

Would you base your design on code posted by a stranger who calls himself TrickyDicky ?

Have you simulated the code? Does it produce the desired result?

Hmmm...  cannot read Verilog, can barely write VHDL. What are the odds Prakash understands the code or how to run the simulator?

-- Bob Elkind

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8,269 Views
Registered: ‎10-05-2010

Would you base your design on code posted by a stranger who calls himself TrickyDicky ?

I would! But only because that's what we call Dick Smith, who originally made his fortune in Australia with a chain of electronics stores.

Professor
8,266 Views
Registered: ‎07-21-2009

I would! But only because that's what we call Dick Smith, who originally made his fortune in Australia with a chain of electronics stores.

1.  Dick Smith's wealth has nothing to do with FPGA (or VHDL) design, but perhaps his eccentricity does.  :)

2.  Dick Smith's life of hard work and success does not help Prakash prosper as a designer.

Just my two (US) cents.

-- Bob Elkind

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4. Do not post a new topic or question on someone else's thread, start a new thread!
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Participant
8,259 Views
Registered: ‎08-17-2011

Hi experts,

First,  I had tried to simulate the code with only dval. Please refer the simulation screen shot. There is no dval  of 3.32 usec pulse generated. dval signal shows as undetermined while simulation. please check the attachment.

Here is the VHDL Code for only Dval generation:

*********************************************

entity strobe_pulse_generation is

port ( clk16M6 : in std_logic;

dval : out std_logic);

end strobe_pulse_generation;

architecture Behavioral of strobe_pulse_generation is

signal counter: std_logic_vector(6 downto 0);

signal enable1u66: std_logic;

begin

process(clk16M6)

begin

if rising_edge(clk16M6) then

if counter >= 54 then

counter <= "0000000"; --(others => '0');

else

counter <= counter + 1;

end if;

end if;

end process;

enable1u66 <= '1' when counter = 0 else '0';

process(clk16M6)

begin

if rising_edge(clk16M6) then

if counter < 28 then

dval <= '1';

else

dval <= '0';

end if;

end if;

end process;

end behavioural;

********************************************;

Here is the testbech code for the Dval generation:

***********************************************

ENTITY strobe_pulse_generation_tb IS

END strobe_pulse_generation_tb;

ARCHITECTURE behavior OF strobe_pulse_generation_tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT strobe_pulse_generation

PORT(

clk16M6 : IN std_logic;

dval : OUT std_logic

);

END COMPONENT;

--Inputs

signal clk16M6 : std_logic := '0';

--Outputs

signal dval : std_logic := '0';

-- Clock period definitions

constant clk16M6_period : time := 60.24 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: strobe_pulse_generation PORT MAP (

clk16M6 => clk16M6,

dval => dval

);

-- Clock process definitions

clk16M6_process :process

begin

clk16M6 <= '0';

wait for clk16M6_period/2;

clk16M6 <= '1';

wait for clk16M6_period/2;

end process;

end;

***********************************

Thanks,

V. Prakash

Professor
8,254 Views
Registered: ‎07-21-2009
• Since DVAL is derived from COUNTER, looking at COUNTER in your simulation might be useful.
• If COUNTER is mis-behaving, then try looking at only the LSB (bit<0>) of COUNTER.
• If the single flip-flop for COUNTER<0> is misbehaving, you have chased the problem down to a single register with very few inputs.  Is it initialised or reset to a known value at any time in the simulation?

Sounds like the clock is not connected to the design, or uninitialised state.

-- Bob Elkind

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