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Participant prakashvenugopal
Participant
7,266 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts,

 

      I had added the 7 bit counter in the simulation screen. Please look at the simulation screen shot. All q[6:0] are in undetermined state  Please refer the attachment.

 

 

VHDL code:

*************************************************************

entity strobe_pulse_generation is

port ( clk16M6 : in std_logic;

Q : out std_logic_vector(6 downto 0);

dval : out std_logic);

 

end strobe_pulse_generation;

 

architecture Behavioral of strobe_pulse_generation is

 

signal counter: std_logic_vector(6 downto 0);

signal enable1u66: std_logic;

 

begin

process(clk16M6)

begin

if clk16M6 ='1' and clk16M6'event then

if (counter >= 54) then

counter <= "0000000";--(others => '0');

else

counter <= counter + 1;

end if;

end if;

end process;

Q <= counter;

 

enable1u66 <= '1' when counter = 0 else '0';

 

 

process(clk16M6)

begin

if clk16M6 ='1' and clk16M6'event then

 

if (counter < 28) then

dval <= '1';

else

dval <= '0';

end if;

end if;

end process;

end Behavioral;

********************************************************

 

 

 

Test bench code:

*********************************************************

ENTITY strobe_pulse_generation_tb IS

END strobe_pulse_generation_tb;

 

ARCHITECTURE behavior OF strobe_pulse_generation_tb IS

 

-- Component Declaration for the Unit Under Test (UUT)

 

COMPONENT strobe_pulse_generation

PORT(

clk16M6 : IN std_logic;

Q : out std_logic_vector(6 downto 0);

dval : OUT std_logic

);

END COMPONENT;

 

 

--Inputs

signal clk16M6 : std_logic := '0';

 

--Outputs

signal dval : std_logic := '0';

 

signal Q : std_logic_vector(6 downto 0) := "0000000";

 

-- Clock period definitions

constant clk16M6_period : time := 60.24 ns;

 

BEGIN

 

-- Instantiate the Unit Under Test (UUT)

uut: strobe_pulse_generation PORT MAP (

clk16M6 => clk16M6,

Q => Q,

dval => dval

);

 

-- Clock process definitions

clk16M6_process :process

begin

clk16M6 <= '0';

wait for clk16M6_period/2;

clk16M6 <= '1';

wait for clk16M6_period/2;

end process;

 end;

 

*******************************************************

 

The letters which is marked in bold are statements which is added for counters to be added to the simualtion.

 

Thanks,

V. Prakash

 

 

 

 

 

dval_with_counter.JPG
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Teacher eteam00
Teacher
7,263 Views
Registered: ‎07-21-2009

Re: Reading and Writing

Did you read the last line of my previous post?  hint: uninitialised state

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant prakashvenugopal
Participant
7,257 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts,

 

       From the simulation screen shot, we found 16m6 clock is running continuously. dval and q[6:0] are in uninitialised state 'U'.We have to initialise that using a '0'. ? How to iniatialise that? Please let me know.

 

Thanks,

V. Prakash

 

 

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Participant prakashvenugopal
Participant
7,244 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Expert,

 

       Can you please explain in details on your last post. hint: uninitialised state

 

Thanks,

V. Prakash

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Scholar joelby
Scholar
7,240 Views
Registered: ‎10-05-2010

Re: Reading and Writing

In ISim, uninitialised registers take on the state U. You can't increment a counter if it's uninitialised - what's the value of "uninitialised plus one"?

 

Initialise your counter register, and perhaps every other register, to some known value.

Participant prakashvenugopal
Participant
7,236 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Expert,

 

               After initialising the counter and dval to a known value, i am able to simulate the dval pulse of 3.32 usec. Simulator screen shot to your reference. Now i will proceed to simulate the Lval Pulse.

 

Thanks,

V. Prakash

dval_3.32usec_simulation.JPG
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Participant prakashvenugopal
Participant
7,224 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts,

 

        I had simulated the dval and lval pulse.

Dval --> on time= 1.66 usec and off time= 1.66 usec (3.32 usec)

Lval --> on time = 849.9 usec and off time = 146.02 usec is achieved.

Please refer the dval and lval pulse on the simulation screen shot. In this, during lval raise, dval is also raising.

Please refer the comm. interface pulse timing diagram, during lval raise, dval is in falling edge. how to do this? please let me know.

 

Here is the VHDL code for dval and lval generation:

************************************************

entity strobe_pulse_generation is
port ( clock : in std_logic := '0';
       Q : out std_logic_vector(6 downto 0);
       dval : out std_logic := '0';
   lval : out std_logic := '0');
end strobe_pulse_generation;  

architecture Behavioral of strobe_pulse_generation is

  signal counter: std_logic_vector(6 downto 0) := "0000000";
signal enable1u66: std_logic;
signal lvalstate : std_logic := '0';
signal lvalcount : unsigned (7 downto 0):= "00000000";

  begin
process(clock)
begin
  if clock ='1' and clock'event then
    if (counter >= 54) then
      counter <=  "0000000";
    else
      counter <= counter + 1;
    end if;
  end if;
end process;
Q <= counter;  

enable1u66 <= '1' when counter = 0 else '0';  


process(clock)
begin
if clock ='1' and clock'event then

      if (counter < 28) then
      dval <= '0';
    else
      dval <= '1';
    end if;
  end if;
end process;

 
process(enable1u66)
begin
if (enable1u66 = '1') then
case(lvalstate) is


when '0' =>                             -- Keep LVAL low for 44 cycles
if (lvalcount = 43) then               -- LOW period is over
lvalstate <= '1';
lval <= '1';
lvalcount <= "00000000";            -- reset the counter
else
lvalcount <= lvalcount + 1;
end if;  

 

when '1' =>                                      -- Keep LVAL high for 256 cycles
if (lvalcount = 255)  then                                    --HIGH period is over
lvalstate <= '0';
lval <= '0';
lvalcount <= "00000000";    -- reset the counter
else
lvalcount <= lvalcount + 1;
end if;  

 

when others =>
lvalcount <= "00000000";
      
end case;
end if;
end process;
   end Behavioral;    

********************************************************************


thanks,

V. Prakash

dval_and_lval_generation.JPG
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Participant prakashvenugopal
Participant
7,221 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi experts,

 

          Please refer the attached comm. interface diagram for during lval raise, the dval is in fall.

 

thanks,

V. Prakash

Comm. Interface_16m6.jpg
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Teacher eteam00
Teacher
7,218 Views
Registered: ‎07-21-2009

Re: Reading and Writing

Please refer the dval and lval pulse on the simulation screen shot. In this, during lval raise, dval is also raising.

Please refer the comm. interface pulse timing diagram, during lval raise, dval is in falling edge. how to do this? please let me know.

 

Prakash,

 

You have big trouble:  You don't understand your own code.  Forget the LVAL and DVAL pulses.  You need to learn how logic gates and registers work, and how to describe these basic logic functions in VHDL.

 

How are you going to learn this?

Until you learn these things, you are completely dependent on others who write code for you, instead of you writing your own code.

 

I was doing you no favours by writing code for you.  I should have realised that you were using us (and edaboard) to avoid the effort to learn these skills for yourself.  I apologise for this, this was a mistake.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
Teacher eteam00
Teacher
7,212 Views
Registered: ‎07-21-2009

Re: Reading and Writing

Please refer the dval and lval pulse on the simulation screen shot. In this, during lval raise, dval is also raising.

Please refer the comm. interface pulse timing diagram, during lval raise, dval is in falling edge. how to do this? please let me know.

 

Look through your code.

 

  • in which lines are DVAL changing from 0 to 1, and from 1 to 0?
  • what logic terms control DVAL value?
  • what logic terms control when DVAL value changes?
  • in which lines are LVAL changing from 0 to 1, and from 1 to 0?
  • what logic terms control LVAL value?
  • what logic terms control when LVAL value changes?

Let's see if we can learn a thing or two about how logic works and understanding VHDL.  Are you ready to learn?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant prakashvenugopal
Participant
7,169 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts,

 

if counter < 28 then
dval <= '1';
else

dval <= '0';
end if;

 

This can be chaged to:

 

if counter < 28 then
dval <= '0';
else

dval <= '1';
end if;

 

am i right? Please verity.

 

Thanks,

V. Prakash

 


 

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Scholar joelby
Scholar
7,166 Views
Registered: ‎10-05-2010

Re: Reading and Writing

Why don't you verify it yourself? It'll only take thirty seconds to check in ISim - much faster than you can post to ask on the forum ;)

 

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Participant prakashvenugopal
Participant
7,152 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts,

 

         I checked that in ISIM. For the code, during lval is raising, dval gets fall

 

Thansks,

V.  Prakash

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Participant prakashvenugopal
Participant
7,137 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts,

 

          Now i am able to simulate the dval --> 3.32 usec pulse and lval --> Ontime=849.92 usec and Offtime= 149.02 usec.

But when i check in the board by downloading the bit file. Only dval is generated. there is no required lval is generated.

What may be the cause for the Problem? Please let me know. Please give some idea to debug this lval generation.

Simulation Screen attached for lval. Please refer.

 

Here is the VHDL code written:

 

entity strobe_pulse_generation is
port ( clock : in std_logic := '0';
       Q : out std_logic_vector(6 downto 0);
       dval : out std_logic := '0';
   lval : out std_logic := '0');


end strobe_pulse_generation;   architecture Behavioral of strobe_pulse_generation is   signal counter: std_logic_vector(6 downto 0) := "0000000";
signal enable1u66: std_logic;
signal lvalstate: std_logic := '0';
signal lvalcount: std_logic_vector (7 downto 0):= "00000000";   begin
process(clock)
begin
  if clock = '1' and clock'event then
    if (counter >= 54) then
      counter <=  "0000000";--(others => '0');
    else
      counter <= counter + 1;
    end if;
  end if;
end process;
Q <= counter;
enable1u66 <= '1' when counter = 0 else '0';  

 

process(clock)
begin
if clock ='1' and clock'event then
    if (counter < 28) then
      dval <= '1';
    else
      dval <= '0';
    end if;
  end if;
end process;  
process(enable1u66)
begin
if (enable1u66 = '1') then
case(lvalstate) is
when '0' =>                             -- Keep LVAL low for 44 cycles
if (lvalcount = 43) then
                           -- LOW period is over
lvalstate <= '1';
lval <= '1';
lvalcount <= "00000000";            -- reset the counter
else
lvalcount <= lvalcount + 1;
end if;   when '1' =>                                      -- Keep LVAL high for 256 cycles
if (lvalcount = 255)  then
                              --HIGH period is over
lvalstate <= '0';
lval <= '0';
lvalcount <= "00000000";    -- reset the counter
else
lvalcount <= lvalcount + 1;
end if;   when others =>
lvalcount <= "00000000";
      
end case;
end if;
end process;

end Behavioral;    


 

Thanks,

V. Prakash

 

 

 

 

simulation_lval.JPG
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Scholar joelby
Scholar
7,133 Views
Registered: ‎10-05-2010

Re: Reading and Writing

Double check that your ping constraint for lval is correct. You can't always trust the user manual to be right, so it's sometimes worth referring to the schematic diagram too.

 

Send some of the other test signals whose behaviour you understand out to pins, such as enable1u66 and a few of the LSBs of your counter. Or use ChipScope Pro to monitor all of these and compare it to your simulation.

 

 

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Teacher eteam00
Teacher
7,131 Views
Registered: ‎07-21-2009

Re: Reading and Writing

There are a number of things you can check.

 

If you have never checked the LVAL pin before, and proven that the pin assignment and board layout are correct, then the obvious possibilities are:

 

  • board layout error
  • pin assignment error
  • you are probing the wrong FPGA pin

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant prakashvenugopal
Participant
7,116 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts,

 

       I am using avnet spartan 3A evaluation board.

As you suggest, i had checked the enable1u66 signal taking out to the Port pin-->on time= 130 Ns and off time= 3.3 usec

dval port pin is working with 3.3 usec pulse. so I had checked the dval and lval swapped with the port output pins. But still dval  pulse is coming out as 3.3 usec, lval is coming out as  ON time= 4 usec and Off time= 77 usec something like this.? 

There is no chance of board layout error, pin assignment. and also i am probing the FPGA pin correctly. What could be the cause for this problem.?

 

Thanks,

V. Prakash

 

 

 

          

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Teacher eteam00
Teacher
7,114 Views
Registered: ‎07-21-2009

Re: Reading and Writing

Well, that is an improvement.  You first reported that there was no pulse output on LVAL, and now you see a pulse output on LVAL.

 

Now you need to change the logic which is controlling LVAL, correct?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant prakashvenugopal
Participant
7,111 Views
Registered: ‎08-17-2011

Re: Reading and Writing

Hi Expert,

 

         Yes. You are right. Now i have to look into the lval generation logic part.

 

Lval Generation Code:

 

process(enable1u66)
begin
if (enable1u66 = '1') then
case(lvalstate) is
when '0' =>                             -- Keep LVAL low for 44 cycles
if (lvalcount = 43) then
                                                   -- LOW period is over
lvalstate <= '1';
lval <= '1';
lvalcount <= "00000000";            -- reset the counter
else
lvalcount <= lvalcount + 1;
end if;  

when '1' =>                                      -- Keep LVAL high for 256 cycles
if (lvalcount = 255)  then
                              --HIGH period is over
lvalstate <= '0';
lval <= '0';
lvalcount <= "00000000";    -- reset the counter
else
lvalcount <= lvalcount + 1;
end if;


  when others =>
lvalcount <= "00000000";
      
end case;
end if;
end process;

**************************************

 

For every 3.3 usec, the enable1u66 gets high. after that, we are checking the lval state. Inital value of lval state = '0', lval = '0'

So it will get into the Case '0' => in this, when lval count = 43,  lval <= '1' and lvalcount = 00. here case state changed to '1'

this will keep lval low for 43 count x 3.32 usec = 149.76 usec.

            In case '1' => when lval count = 255, lval <= '0' and lvalcount =00. here case state changed to '0'.

This will keep lval high for 255 count x 3.32 usec = 846.6 usec. so this will be done continously. Logic is found to be correct. I am able to simulate the same. But it is not working as required pulse ? Is there any mistake here.?

 

Thanks,

V. Prakash

 

 

 


 

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Scholar joelby
Scholar
7,107 Views
Registered: ‎10-05-2010

Re: Reading and Writing

I'm struggling to follow along closely enough, but the enable1u66 signal was originally intended to be asserted once every 1.66 usec, not every 3.32 usec (the clue is right there in the name). However anything is possible now and it was impossible to see what was going on at the usec scale from from your last screenshot.

 

With a very simple circuit like this, the simulation will almost certainly reflect the true output. From your last posts, it's not really clear if you're getting an incorrect lval pulse or no lval at all.

 

If lval is incorrect: look at the simulation, zoom in, and verify all timing precisely. Look at what the counter value is at the instant when it changes. If it changes at the wrong time, update the counter check logic to match exactly what you want.

 

If there's no lval output: post your UCF and tell us exactly which pins on the Avnet Spartan-3A board you're probing.

 

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Teacher eteam00
Teacher
6,930 Views
Registered: ‎07-21-2009

Re: Reading and Writing

process(enable1u66)
begin
if (enable1u66 = '1') then

 

The signal enable1u66 is not a clock, and it is not a latch enable.

Look at your previous code, and remember how a clocked process is constructed in VHDL.

It looks like this mistake originates from incomplete Verilog => VHDL code translation.

 

Looking at the Verilog code I posted, the LVAL signal changes state on the same clock edge as DVAL's 1=>0 transition.  If I am correct, the code should work as specified by Prakash -- if it is translated correctly from Verilog to VHDL.

 

Prakash, this problem demonstrates that you do not yet understand the language you are reading, copying, and editing.  This takes time, but it is absolutely essential that you learn

 

  • what are process sensitivity lists and what do they mean
  • what is a register, what is a clock, what is a clock enable
  • what does if clk'event mean

These are basic constructs of the VHDL and Verilog language.  You shouldn't expect to progress very far at all until you can write code on your own, with an understanding of how it works, rather than simply copying words and phrases without an understanding of their meaning.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
0 Kudos
Teacher eteam00
Teacher
6,923 Views
Registered: ‎07-21-2009

Re: Reading and Writing

I'm struggling to follow along closely enough, but the enable1u66 signal was originally intended to be asserted once every 1.66 usec, not every 3.32 usec (the clue is right there in the name).

 

I believe that -- at some point -- the VHDL code was (poorly) translated from Verilog code which I posted, which was based heavily on your (joelby's) code.  The enable1u66 signal is instantiated in my code (after torturing *your* code) as follows:

 

wire enable1u66// pixel-rate, single-cycle clock enable pulse

// Assert the clock enable every 55 cycles, a pixel-rate pulse
assign enable1u66 = (counter == 7'd28);

 

So enable1u66 has become a 3.3uS period signal.

 

By the way, I just now edited post #17 in this thread to add the highlighted comments:

 

// Assert the clock enable every 55 cycles, a pixel-rate pulse
// enable1u66 clock enable pulse coincides with last clock cycle before dval 1=>0 transition
assign enable1u66 = (counter == 7'd28);
always @(posedge clk16M6)  dval <= (counter < 7'd28);  // dval has 28/27 duty cycle

 

and

 

always @(posedge clk16M6)
  if (enable1u66)  // advance at pixel rate, output changes are coincident with dval falling edge
    case(lvalstate)

 

Hope this clears up a detail or two.

 

However anything is possible now and it was impossible to see what was going on at the usec scale from from your last screenshot.

 

As noted previously in this thread, Prakash is not yet ready to retire his VHDL language primer.  This will all sort itself out, given enough time and patience.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher rcingham
Teacher
6,918 Views
Registered: ‎09-09-2010

Re: Reading and Writing

"Prakash is not yet ready to retire his VHDL language primer."

Too right. The sensitivity list for that LVAL process is badly wrong if it is meant to be a combinational process, and if it meant to be a clocked process it is all just plain wrong.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Teacher eteam00
Teacher
6,902 Views
Registered: ‎07-21-2009

Re: Reading and Writing

The sensitivity list for that LVAL process is badly wrong if it is meant to be a combinational process, and if it meant to be a clocked process it is all just plain wrong.

 

In the predecessor verilog code from which this was translated, the process in question is a clocked process.  The translation to VHDL shows a serious lack of understanding of the VHDL language at the most basic level.

 

Prakash, you need to learn and understand

  • what is a register (or flip-flop)
  • how a register works
  • how is a register used
  • how to describe a register (or flip-flop) in VHDL
  • the meaning of the various parts of the VHDL register description
  • the usage of the various parts of the VHDL register description

There is much more to learn, of course, but these are bits which have been shown lacking through your work in this thread.

 

As you go through VHDL learning exercises, you should ask yourself each of the 6 points listed above until these questions are so well understood that they require little thought.

 

Here is a web page with a few links to online VHDL learning tools.

 

You will learn more efficiently and more effectively with an instructor or guide -- someone to look over your shoulder and correct you in person.

 

-- Bob Elkind

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Participant prakashvenugopal
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Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts, Yes. You are right. The clocked process should have a clock in the process sensitivity list. dval and lval should get sychronised with the same clock. Please refer the attachement Lval timing. process(clock) begin if (enable1u66 = '1') then case(lvalstate) is when '0' => -- Keep LVAL low for 44 cycles if (lvalcount = 43) then -- LOW period is over lvalstate <= '1'; lval <= '1'; lvalcount <= "00000000"; -- reset the counter else lvalcount <= lvalcount + 1; end if; when '1' => -- Keep LVAL high for 256 cycles if (lvalcount = 255) then --HIGH period is over lvalstate <= '0'; lval <= '0'; lvalcount <= "00000000"; -- reset the counter else lvalcount <= lvalcount + 1; end if; when others => lvalcount <= "00000000"; end case; end if; end process; When i placed the clock in the process sensitivity, the observation is like this: Dval --> perfect 3.32 usec pulse Lval --> On time= 424.3 usec and Off time = 73.66 usec But Required Lval --> On time= 3.32 usec x 256 = 849.9 usec , off time = 3.32 usec x 43 = 146.08 usec see, Half the time of LVAL ontime = 849.9/2 = 424.95 usec is obtained while simulation. Half the time of Lval off time = 146.08/2 = 73.6 usec is obtained while simulation. Thanks, V. Prakash
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Participant prakashvenugopal
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Registered: ‎08-17-2011

Re: Reading and Writing

Hi Experts,

 

Yes. You are right.The clocked process should have a clock in the process sensitivity list. dval and lval should get sychronised with the same clock. Please refer the attachement Lval timing.

 

 

process(clock)

begin

if (enable1u66 = '1') then

case(lvalstate) is

when '0' => -- Keep LVAL low for 44 cycles

if (lvalcount = 43) then -- LOW period is over

lvalstate <= '1';

lval <= '1';

lvalcount <= "00000000"; -- reset the counter

else lvalcount <= lvalcount + 1;

end if;

when '1' => -- Keep LVAL high for 256 cycles

if (lvalcount = 255) then --HIGH period is over

lvalstate <= '0';

lval <= '0';

lvalcount <= "00000000"; -- reset the counter

else lvalcount <= lvalcount + 1;

end if;

when others =>

lvalcount <= "00000000";

end case;

end if;

end process;

 

When i placed the clock in the process sensitivity, the observation is like this:

Dval --> perfect 3.32 usec pulse

Lval --> On time= 424.3 usec and Off time = 73.66 usec

 

But Required Lval --> On time= 3.32 usec x 256 = 849.9 usec , off time = 3.32 usec x 43 = 146.08 usec

 

see, Half the time of LVAL ontime = 849.9/2 = 424.95 usec is obtained while simulation.

Half the time of Lval off time = 146.08/2 = 73.6 usec is obtained while simulation.

 

Thanks,

V. Prakash

lval_generation_divided.JPG
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Teacher eteam00
Teacher
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Registered: ‎07-21-2009

VHDL lesson from a Verilog guy...

This should look familiar:

 

process(clock)
  if clock ='1' and clock'event then

 

What does the second line mean?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Participant prakashvenugopal
Participant
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Registered: ‎08-17-2011

Re: VHDL lesson from a Verilog guy...

Hi Expert,

 

               Yes. You are right. I missed out to check the raising edge of the clock in lval generation.

 

Process(clock)

if (clock = '1' and clock'event)

 

Now i am clear:

clock'event is used to specify the change in clock value and clock=1 is the high state of the clock. When they are both used together it signifies rising edge of the clock.

 

Thanks,

V. Prakash

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Teacher rcingham
Teacher
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Registered: ‎09-09-2010

Re: VHDL lesson from a Verilog guy...


@eteam00 wrote:

This should look familiar:

 

process(clock)
  if clock ='1' and clock'event then

 

What does the second line mean?

 

-- Bob Elkind


We grizzled VHDL pros tend to use

if rising_edge(clock) then

 

end if;

instead...

There is also a falling_edge() function.


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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Historian
Historian
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Registered: ‎02-25-2008

Re: VHDL lesson from a Verilog guy...


@rcingham wrote:

We grizzled VHDL pros tend to use

if rising_edge(clock) then

 

end if;

instead...

There is also a falling_edge() function.



Who you callin' "grizzled," Willis?

NOW GET OFF MY LAWN!

 

Oh, wait, I live in the desert. I don't have a lawn.

NOW GET OFF MY DIRT!

 

Seriously, there's actually a Real Good Reason why the rising_edge() function is preferred over the event-detect and test-for-state in the old idiom. It's an exercise left to the reader to learn this Real Good Reason.

----------------------------Yes, I do this for a living.
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