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miro_atc
Visitor
Visitor
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Registered: ‎07-26-2011

S6 IODELAY2 Calibration

I have tried to implement Phase Detector and Board Descew as explained in xapp1064 for a single ended signal with frequency around 66MHz. The state machine waits some time and then issues a calibrate command to both master and slave iodelays. The busy gets high and never goes down again.

 

I can search for bugs in my code, however after reading all the specs again and again I think everythings works correctly. Perhaps the calibration waits for few short pulses (less than 5.3nS) in my signal. And since the period of my signal is much longer it will never get calibrated, right??

 

 

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eteam00
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Instructor
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Registered: ‎07-21-2009

You are describing the problem as if we are in the same room with you and as if we can read and understand your code.

 

Unfortunately, we are not in the same room with you and we have not seen your code and we do not understand what your design is trying to do.  Please be more specific when you are mention "the state machine" and "the busy" and "few short pulses" and "everything works".

 

Trying to reconstruct your design and your code from the clues you have given us is very time-consuming and error-prone, so please tell us:

 

  • what are you trying to do
  • how are you doing it
  • what tests have you run
  • what works
  • what doesn't work

 

It will be much easier to help you with a bit more information.

 

-- Bob Elkind

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mcgett
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Registered: ‎01-03-2008

>  signal with frequency around 66MHz.....issues a calibrate command to both master and slave iodelays

 

66 MHz (and likely 66 Mbps) is too slow for the IODELAY2 calibration function (see table 39 in the Spartan-6 data sheet).

 

There is no need to use these high speed capture techniques with signals that run this slow.

 

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miro_atc
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Registered: ‎07-26-2011

>66 MHz (and likely 66 Mbps) is too slow for the IODELAY2 calibration function

 

Thank you mcgett, this was my assumption too and now it is confirmed :-) 

 

@Bob,

I just wanted to confirm that the problem is due to the low frequency not the vhdl.  That's why I was not so specific...

 

Here is what I have:

I have a clock and data-out line sent to a target device and I have data-in line back from the device. The clock must be programable so the user can select as low as few kHz and as high as it can get. Up to 20-30Mhz I don't need to deskew the signal. Above 188MHz I can use the phase detector and deskew logic probably.

 

But the question is what I do in between?

 

Note that the delay is unknown and I am quite sure there is no way to capture a signal in the 100MHz range without deskew logic.

 

Btw from the very beginning I have expected that the IODelay2 auto calibration won't work. So I have plan "B", and I hope that the Phase Detector logic will work with any frequency as long as I can provide the following:

 

1) fixed delay between the master and slave IODelays sampling points, which is not more than the 1/2 from the data eye and not less than some critical minimum.

2) In order to process the VALID and INCDEC commands I must be able to move both sampling point across the entire clock period of my clock (whatever the frequency is).

 

Now, without calibration I cannot measure the data eye. But I think this is not that big problem because I can specify that it must be at least 2nS. If the real window is not that much open it will not work anyway. 

The real problem is with the second requirement. Let say I use 10ns clock period but due to the limitation of the delay lines I cannot have delays more than 5.3nS. However if the eye happens to be in the first 1/4 of the clock - everything is OK. And I can check that it is OK. Now let's say the eye is not in the first 1/4 so I am supposed to increase the delays. 

But instead I can phase shift my IO clock with 90 degrees... If this doesn't work I can try 180 and then 270 deg.... So with the variable phase shift capabilities I can increase the delay range, or at least I hope so ;-)

 

Do you think this can work?

 

Thanks,

Miro

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

Here we go...  This is off the top of my head, not completely thought out, so it may be more or less brain-damaged.

 

Generate a 333MHz clock for fabric logic, near the frequency limit for Spartan-6 devices, in one PLL.

 

Divide this 333MHz clock to a timebase TIMEBASE1 which can be used to generate the clock frequency you desire.

TIMEBASE1 will be used by a second PLL.

TIMEBASE1 must have 50% duty cycle.

TIMEBASE1 frequency must fall within a 2:1 frequency range.

 

The second PLL will use this TIMEBASE1 to generate an IO clock in the range of 500MHz to 1GHz, and a (1/8) fabric clock in the range of 62.5MHz to 125MHz.  Both of these clocks will be locked to TIMEBASE1The IO clock frequency is an even integer multiple of the desired serial data rate.

 

Using an OSERDES2 block and fabric logic, the SERIAL_CLOCK for the external device is generated.  The frequency range of SERIAL_CLOCK is DC to 500MHz (upper limit of I/O clock frequency divided by 2).

 

Input serial data rate is the same as SERIAL_CLOCK frequency.  IDELAY2 blocks align the serial data to the IO clock, and the ISERDES2 blocks deserialise the data by 1:8.  It is entirely up to the fabric logic to word-frame the deserialised data.

 

For low-frequency operation, the serial data will be grossly over-sampled and will need to be decimated.  Because the fabric logic and the ISERDES2 blocks and serial input data and SERIAL_CLOCK are all locked to the same TIMEBASE1 timebase, everything works.

 

The dividers for generating TIMEBASE1, for generating SERIAL_CLOCK, and for word framing (and decimating) input data can be stored in a lookup table for design simplicity.

 

This approach, in sum, uses a highest usable even integer multiple of the desired serial data frequency -- within a single octave range, to keep the second PLL happy -- to run the design.  This keeps the IOCLOCK within the operating range for the IDELAY2 blocks in variable delay mode.

 

I haven't thought this through, so it may need some review and some tweaking.  Comments and revisions are welcome.

 

NOTES:

  • The generated timebases are no better (accurate, stable, precise) than the source clock for the first PLL.
  • The single-octave (2:1) range for TIMEBASE1 may be unnecessarily restrictive, but it should be workable.
  • It greatly simplifies the logic to keep the frequency ratio between the IO clock and SERIAL_CLOCK an even integer.

 -- Bob Elkind

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miro_atc
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Registered: ‎07-26-2011

Thank you Bob,

 

I am afraid I haven't told you the whole story... In fact the interface is jtag/swd and what I am doing is a debugger. We are many years on the marked and the current version works with approach which is quite similar to what you suggest.

At startup we put the targets in bypass mode and then we start measurement sequence. As you can imagine we don't have control over the cable length, buffers etc, so the delay can vary a lot. Anyway, we send a known pattern and we try various capture offsets until we get a correct reception.

 

This works for many targets. But unfortunately there are few exceptions. Some targets are not quite synchronous or they have different internal paths. When we put them in a bypass mode or select the standard TAP registers they don't show any delay. But when accessing some internal registers we got a delay. I suppose this is due to the synchronization between their CPU clock domain and the jtag's TCK domain. Typically this delay is small compared with the clock period, but since we deal with poor signal integrities our eye window is quite limited.

So we calibrate to one delay and it can change on the fly. The problem is that we have no clue what data to expect so we can't catch the errors.

 

That's why I look at the Phase Detector feature. I hope I can use it to dynamically adjust the delays without knowing the data. Of course in the beginning I will have a coarse delay measurement using a special data pattern.

 

So the question is about the Phase Detector logic – it is not clear from the documentation will it work for low speed or not?

 

If it does not work I will try something like your approach Bob, but without IODelays2s - they are not stable (temperature etc).

 

Miro

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

So the question is about the Phase Detector logic – it is not clear from the documentation will it work for low speed or not?

 

What mcgett wrote in post #3 in this thread is correct.  The DS162 datasheet specification for F(mincal) in Table 39 is unambiguous.  The delay range of IDELAY block is limited, and this imposes a maximum limit on the IOCLOCK period (i.e. a minimum IOCLOCK frequency requirement).

 

but without IODelays2s - they are not stable (temperature etc).

 

What is your alternative?  The delays of the input buffers, input registers, and clock buffers are also 'not stable' over process, temperature, and voltage.  That's the problem which the IDELAY2 blocks were designed to overcome.  The countermeasure for P/T/V variations in IDELAY2 blocks is calibration.  This only matters at high bit rates, of course.

 

It sounds like you understand the underlying issues quite well.  I'm looking forward to your description of your intended design approach.

 

-- Bob Elkind

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Summary:
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miro_atc
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Registered: ‎07-26-2011

>What is your alternative?

 

My idea is:

 

1)  I will set the slave IODelay to zero delay and the master to delay 1/2X, where "X" is my guess for the expected eye width.

2) I will use the standard Phase Detector logic, which is suppoused to tell me if the there is VALID edge and if I have to change the delay (INCDEC).

3) I will follow the commands but I will also keep track of the requested increment & decrement steps.

if the eye is close to the beginning of my clock period eventualy I will lock it. 

Otherwise I suppouse the phase detector will request more and more inrease in the delays. However when I reach the maximum I will return the delays to initial values and I will phase shift the IO clock. Then I will restart the search.

 

In sum:  I will use clock phase shifting as a coarse delay and then IODelay2s for fine tunning.

 

About the "X" guess... on startup I willl brute force many values and will get the range for X, so in a way this will not be a wild guess but something like a measuremnt. 

 

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eteam00
Instructor
Instructor
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Registered: ‎07-21-2009

The IDELAY2 blocks are variable only in modes which require providing an IOCLOCK and IDELAY2 calibration, with an IOCLOCK frequency range bounded by F(mincal) (DS162 Table 39).  This places a 188MHz lower bound on IOCLOCK frequency.

 

Use of the the DCM (rather than PLL) allows the use of the DCM's dynamic phase shift capabilities.  This places a 375MHz upper bound on IOCLOCK frequency.

 

You can extend the serial bit rate range and IOCLOCK frequency range beyond 375MHz by feeding the DCM output to a PLL for fixed frequency multiplication.

 

Can you explain how you would use coarse and fine de-skew adjustment range which exceeds the IOCLOCK period?  In other words, in what circumstances would the IDELAY2 dynamic delay adjust range of 1 IOCLOCK period be insufficient?

 

-- Bob Elkind

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Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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miro_atc
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Registered: ‎07-26-2011

>The IDELAY2 blocks are variable only in modes which require providing an IOCLOCK and IDELAY2 calibration


Are you sure? 

In the way I understand the specs no clock is required at all during the normal operation of IODELAY2. It has its own ring oscillator which drives a counter...

The IOCLOCK is used (as reference) only during calibration, but I am not going to use the calibration. Since the decision when to switch between calibration mode and normal mode is taken from a state machine in the fabric I see no problem to prevent it from going into calibration mode.

 

 


>Can you explain how you would use coarse and fine de-skew adjustment range which exceeds the IOCLOCK period?

 

Let's say I use quadrant phase shift so I will have 4 sampling ranges and in each range I also have 256 possible delays. In total 1k possible sample points.  Well, depending on the frequency some of the points may overlap but that is OK.

 

Now after power up I will place the jtag chain in bypass mode. Then I will do a test with known data pattern for each of these sampling points. By analyzing the bad and good results the software will get the picture of the eye.

Then I will select the best quadrant and the default values for the slave and master IODELAYs.  This test will actually replace the built-in calibration.

 

From this point I will enable the Phase Detector logic. If the skew change or the temperature change I hope I will get proper INCDEC command from this logic and I will change the delays accordingly... 

 

 

 

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eteam00
Instructor
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Registered: ‎07-21-2009

In the way I understand the specs no clock is required at all during the normal operation of IODELAY2. It has its own ring oscillator which drives a counter...

 

Think about this logically.  In DIFF_PHASE_DETECTOR mode, the input data is sampled twice to determine the input data transition position relative to....  what?  Without a timing reference, how is a "timing adjustment" determination possible?

 

These questions need to be answered before moving on to the JTAG-test-delay-set procedure you described.  You need to come to terms with the need (or absence of need) for an IOCLOCK if using dynamic IODELAY2 adjust.

You may want to re-read the I/O Delay Overview section of UG381.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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miro_atc
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Registered: ‎07-26-2011

I have been busy with other projects, but funally I did some tests... And here are the results and problems:

 

But first a short description.

 

I am trying to read/capture a signal with 120Mbps data rate. The signal is applied to master and slave IODelays and Serdes. The seredes are set to factor 4, so I get something like oversampling at 480MHz. The whole schematic is pretty stanadrd as explained in xap1064. 

 

Of course I have unknown skew which I am trying to desckew. Since my bitrate is too low (<188Mbps) I have disbled the calibration.  So the IODelays are not calibrated. On reset they are both set at zero and then I try to increase the master delay by applying clock enable and INC to the unit. As a result I see that the busy goes high and stays high untill I apply few transtitions in the input stream. Then the busy is deasserted, so it looks like working... 

Howver I do not see any change in the actual data. I have taken  the DATAOUT2 and I check it with osciloscope. Of course one tap is too small so I compare 0 taps and 100 taps and I am using a 4Gbps osciloscope so I should be able to see 1-4nS difference. Unfortunately I do not see any difference...

 

So this is the problem - it looks like the IODelay does not update, altough the BUSY acts exactly as expected...

I know that normally I would have a CAL command and then INC/DEC.  So is it possible to use the IODelay without the automatic calibranion in a DIFF_PHASE_DETECTOR mode ?

 

Dispate this problem - the rest seems to be working.  It turned out that I can get a correct receiption by playing only with the bitslip function. So I can use the oversampling/bitslip for rough deskew. And with the current setup this is enough. 

However it would be great if I can add and fine tunning as well. That's why I need the IODelays. Of course I also need the delay to make some use of the phase detection. I have tested it as well and the VALID output seems working.  But for real usage I need to set a proper distance between the slave and master and then to move both... 

 

 

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