06-17-2010 05:19 AM
Where can I find the required rise/fall time values for the configuration clock pin in spartan 6 devices ? The values are not available in the data sheet "Spartan-6 FPGA Data Sheet: DC and Switching Characteristics".
06-17-2010 07:38 AM
Rise and fall times depend on the IOstandard. Generally, the rise and fall times should be free of glitches, or noise so you do not get double clocking. A sine wave can even be used if it is clean enough.
06-17-2010 11:05 AM
A sinewave is actually an ideal clock waveform, much 'friendlier' than a square wave. (none of those nasty high frequency harmonics, just a clean fundamental frequency waveform!).
As Austin stated, the critical design criteria is to avoid glitches in the clock, and this requires sound practices for routing and terminating the clock net on the circuit board. The configuration user guide (UG380 for S6 devices) has a section on config clock board layout.
As for optimal (which is different from allowable) rise/fall time for the config clock, it's a safe bet to mimic what Xilinx has designed into their devices. In the S6 case, Xilinx has chosen 8mA drive LVCMOS25 IO std for the config clock output from their devices. This should be good guidance for an external config clock source (if it's good enough for Xilinx, it should be good enough for you, right?). The rise/fall time specs for an 8mA LVCMOS25 output are in the technology datasheet (e.g. DS162 in the case of S6). And if your rise/fall time is slower than that spec, you're still probably OK as long as the waveform is monotonic (no glitches) at all loads on the clock run.
- Bob Elkind