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11,684 Views
Registered: ‎06-12-2013

S6 clocking minimum input frequency

Hi,

 

I'm trying to get an 80MHz clock from a 4MHz input clock on an S6SLX9 FPGA. First I tried instantiating a DCM_SP which works in principal but caused error. I assume that these error are caused by the DCM_SP minimum input frequency of 5 MHz as indicated by a timing warning. Is there a primitive I can use to multiple 4MHz?

 

Kind regards

Simon

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Moderator
Moderator
11,669 Views
Registered: ‎01-16-2013

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11,667 Views
Registered: ‎06-12-2013

Ok, thx, this helped me. So, when using PLL or the DLL in the DCM I have the following minimum input frequencies:

 

PLL: 19MHz

DCM/DLL: 5MHz

 

It also says:

When operating independently of the DLL, the DFS supports lower CLKIN_FREQ_DLL frequencies.

 

When only using the DFS I don't have any phase correlation, right? For my design I think this should work.

 

When I want to use the DFS in stand-alone, can I can do this by using a DCM_SP in a certain configuration (i.e. without feedback loop?)

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11,662 Views
Registered: ‎06-12-2013

Ok, below the code I tried. Gives me no timing warning. But apparently my errors on the hardware stay, maybe there is another reason for it. Thx a lot!

 

-------------------------------------------------------------------------------- Clock_Manager : DCM_SP -------------------------------------------------------------------------------- generic map (
CLKDV_DIVIDE => 2.0, -- CLKDV divide value
CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
CLKFX_MULTIPLY => MULTIPLY, -- Multiply value on CLKFX outputs - M - (2-32)
CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
CLKIN_PERIOD => 250.0, -- Input clock period specified in nS
CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
CLK_FEEDBACK => "NONE", -- Feedback source (NONE, 1X, 2X)
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
)
port map (
CLKIN => clk_in,
CLKFX => clk_out,
STATUS => dcm_status_s,
RST => reset_dcm
);
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11,661 Views
Registered: ‎06-12-2013

I forget to mention that "MULTIPLY" is a generic of my entity
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Moderator
Moderator
11,564 Views
Registered: ‎01-16-2013

Hi,

Could you please provide me detail what exact issue now you are facing?

Thanks,
Yash
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Moderator
Moderator
11,550 Views
Registered: ‎02-16-2010

Did you simulate the DCM instantiation? whether it is working fine?

I recommend to use the clocking wizard to generate the instantiation and compare if any update to the parameters is required.
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