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Adventurer
Adventurer
5,500 Views
Registered: ‎05-27-2011

SDRAM SSTL2 and LVCMOS IO

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Hi All,

 

Due to a single-man team and the reams of doc involved during PCB design. We have a PCB issue with the VREF pins for SSTL input. We are interfacing to a Micron SDRAM where the termination resistors, VREF and VTT voltages are all correct. VREF on the FPGA is now unavailable to us due to contension with other ICs connected to the FPGA bank.

 

My thoughts:

 - The SSTL driver uses a normal CMOS inverter output, but requires a 25Ohm series termination. Surely then it doesn't actually need VREF so I can either a) use SSTL if pin is an output, but the tools may issue an error/warning or b) use an LVCMOS driver and the OUT_TERM = UNTUNED_25 series termination constraint to form what would effectively be the same circuit. 

 - The SSTL receiver uses a differential pair with the _N input connected to VREF, it also requires a VREF biased 50Ohm shunt termination. Now VREF is the issue so surely a possible solution would be, to use LVCMOS standard as an input, same 2.5V IO voltage and of cource a 2.5V/2 = 1.25V switching threshold. I can then use IN_TERM = UNTUNED_SPLIT_50 as this creates an effective thevenin input termination of 50Ohm to an effective voltage of 1.25V.

 

Now I suspect I would get the same performance, however getting access to the SDRAM is more important in the short term while PCB re-spin is longer term. The SDRAM should be clocked at 133MHz, therefore to help reduce SI issues due to this non-ideal VREF situation I was going to run the SDRAM at 100MHz, or even 75MHz.

 

Many thanks.

Ed

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Instructor
Instructor
10,243 Views
Registered: ‎08-14-2007

Re: SDRAM SSTL2 and LVCMOS IO

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What FPGA family are you using?  Some newer devices (7-series) allow you to use an internal Vref rather than eating up the pins on the design.  If this is not an option, then you really only need to change the inputs of your design, not the outputs (unless they are bidirectional).  Only inputs or bidirs use Vref for SSTL.  SSTL outputs do not require Vref, so address, RAS, CAS, etc. can still be SSTL even if you don't have a proper Vref connection.

You could try using LVCMOS for inputs, but the threshold voltages for LVCMOS are not very precise, so you would probably lose significant timing margin.

-- Gabor
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2 Replies
Instructor
Instructor
10,244 Views
Registered: ‎08-14-2007

Re: SDRAM SSTL2 and LVCMOS IO

Jump to solution

What FPGA family are you using?  Some newer devices (7-series) allow you to use an internal Vref rather than eating up the pins on the design.  If this is not an option, then you really only need to change the inputs of your design, not the outputs (unless they are bidirectional).  Only inputs or bidirs use Vref for SSTL.  SSTL outputs do not require Vref, so address, RAS, CAS, etc. can still be SSTL even if you don't have a proper Vref connection.

You could try using LVCMOS for inputs, but the threshold voltages for LVCMOS are not very precise, so you would probably lose significant timing margin.

-- Gabor
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Adventurer
Adventurer
5,255 Views
Registered: ‎05-27-2011

Re: SDRAM SSTL2 and LVCMOS IO

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Hi Gabor,

 

Thanks, I've got a full build to pass all constraints. Its a Spartan 6. 

 

For outputs we are using SSTL_II as you mention they do not require VREF. For the inputs I have full compilation using CMOS input drivers, but your right the threshold levels are less procise. I plan on using the 50Ohm termination options to improve the SI of these lines, but of course ensure the issue is resolved in the next board spin.

 

In terms of timing margin, I'm prepared to take the hit while we wait for the longer term PCB re-spin. 

 

The IC can be clocked at 200MHz, we are therefore going to take that timing hit and clock at 100MHz. 

 

Many thanks.

Ed

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