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Scholar embedded
Scholar
8,195 Views
Registered: ‎06-09-2011

SP6 power up sequencing considerations for safe and correct configuration start

Hi all,

 

Just raising this question here to double check it with experts and find out of there is any problem.

I am designing a new board based on SP6 -XC6SLX40FGG474- and other project specifications. Here are my project inputs and constraints to acheive the best power up timing that covers configuration timing needs: 
According to my Regulator -TPS62132- the total ramp time of +3.3V supply would be about 1.6ms. FPGA Flash - a SPI flash for configuration - requires a minimum VCC volatge of 2.7V for receiving any read commands and about 30uS after that, FPGA can issue read commands - starts clocking to read from SPI.
According to the SP6 specification, the minimum voltage of VCCO2 for Config start is 1.65V -Page 7 of ds162.
Furthermore, if TPOR delay time - @ least 5ms in any conditions: Page 54 of ds162 - is grater than
my regulator ramp time from 1.65V to 2.7V I would be sure that I have followed power up timing needed for both
FPGA and SPI. Is there any ohter issue in power up timing that I need to care about?

 

I would appreciate any advice on this issue,

 

Hossein

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5 Replies
Xilinx Employee
Xilinx Employee
8,178 Views
Registered: ‎08-01-2012

Re: SP6 power up sequencing considerations for safe and correct configuration start

As per data sheet the power-up ramp specification is 0.2mS to 50 mS

 

There is no compulsory power-up sequence for Spartan-6

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Scholar embedded
Scholar
8,175 Views
Registered: ‎06-09-2011

Re: SP6 power up sequencing considerations for safe and correct configuration start

 

Where's this been actually said?
I only reffered the page of 54 of ds162, where it deals with TPOR.
Another issue from SP6 datasheets: Although SP6 devices don't need any power up sequencing, designers should care about power up timing requirements of configuration devices:(ug394 Supply sequencing)

 

Regards,

Hossein

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Teacher eteam00
Teacher
8,173 Views
Registered: ‎07-21-2009

Re: SP6 power up sequencing considerations for safe and correct configuration start

See DS162, Table 6:  Power Supply Ramp Time.  Also, see Table 6 Note 2:

 

... Spartan-6 devices do not have a required power-on sequence.

 

-- Bob Elkind

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Teacher eteam00
Teacher
8,171 Views
Registered: ‎07-21-2009

Re: SP6 power up sequencing considerations for safe and correct configuration start

Another issue from SP6 datasheets: Although SP6 devices don't need any power up sequencing, designers should care about power up timing requirements of configuration devices:(ug394 Supply sequencing)

 

Right.  At power-up, if the Spartan-6 device begins master configuration before the SPI configuration device is 'ready' (after powerup), then configuration is likely to fail.  For some board designs and SPI flash memories, for example, an external circuit may be needed to further extend the initial power-on delay before beginning configuration.

 

Does this make sense?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Scholar embedded
Scholar
8,168 Views
Registered: ‎06-09-2011

Re: SP6 power up sequencing considerations for safe and correct configuration start

Hi,

Thank you for your fast reply.
Yes, I know what you mean. I only wanted to know even if with my mentioned design specifications - that was come earlier - I need to postpone configuration start or not? - Yes, FPGA would be getting configuration in Master mode -
Summarizing my design here, I hope you would give comments on that - and I appreciate it so much - please don't discuss general cases!.

    Nominal ramp time of my +3.3V regulator is about 1.6ms  (tps62132)
    10uS after reaching 2.7v - VCCmin of SPI flash - can accept read commands.
    VCCo2 min voltage to start CCLK and configuration is about 1.65V
    A time tPOR after all three supplies reach their respective thresholds, the POR reset is released and the FPGA begins its configuration process.(ug394, p:31)

My conclusion:

I only have to double check the time from 1.65V to 2.7V and if it is less than minimum 5ms - minimum TPOR ds162 table 47 - I would be sure that I don't need external circuit to postpone configuration. finally, as I further mentioned, it is less than 5ms(1.6ms from 0 to +3.3V!.)

Regards,
Hossein

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