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ntropy
Adventurer
Adventurer
7,741 Views
Registered: ‎09-16-2009

SP601 Max Voltage on J13 GPIO Pin

I have a SP601 starter kit board and was wondering if I can place a 15v signal without frying the board.  Thank you for your help.

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13 Replies
mcgett
Xilinx Employee
Xilinx Employee
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Registered: ‎01-03-2008

Don't do this.  You will fry the FPGA.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
ntropy
Adventurer
Adventurer
7,730 Views
Registered: ‎09-16-2009

What do you suggest I do?

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eteam00
Professor
Professor
7,710 Views
Registered: ‎07-21-2009

What do you suggest I do?

  • Well, I suggest consulting the Spartan-6 Datasheet DS162 for maximum IO pin input voltage specification.  See Table 1.  If you exceed this voltage, you risk damaging the FPGA.
  • Then consult the SP601 schematics for VCCO voltage used for the FPGA pins connected to J13 GPIO.  This will guide you to which IOSTANDARDs are available for use.
  • While in the DS162 doc, check the logic input thresholds (VIN for HI/LOW) for the various IOSTANDARDs you can select. See Table 9.  If you violate these voltages (for the IOSTANDARD you select), you risk misinterpreting the logic "1" and logic "0" states of your input signal.

Would you like me to look these up for you, or do you want to look these up for yourself?

 

-- Bob Elkind

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ntropy
Adventurer
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Registered: ‎09-16-2009

Looking at Spartan-6 Dataset DS162 it seems that the max input is 3.3V.

 

Looking at the SP601 schematic for the J13 GPIO, I/Os pins support LVCMOS25 signaling--3.3v.


Looking back at Spartan-6 Datasheet DS162 Table 9 results:

I/O Standard: LVCMOS25

VIL Min:–0.5

VIL Max:0.7

VIH Min:1.7

VIH Max:4.1

VOL Max: 0.4

VOL Min: VCCO – 0.4

 

It looks like the max input is around 4v without hurting the board, is this correct?  If I have a 15v signal input, is there an internal way to regulate the power coming on, or do i just need to create a voltage divider to drive down the signal?

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eteam00
Professor
Professor
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Registered: ‎07-21-2009

Looking at the SP601 schematic for the J13 GPIO, I/Os pins support LVCMOS25 signaling--3.3v.

The GPIO pins go to IO banks with VCCO=2.5V (not 3.3V).  See page 2 and 3 of the board schematics.

It looks like the max input is around 4v without hurting the board, is this correct?

To be precise, 4.1V for commercial temp range parts.  DS162 Table 1

If I have a 15v signal input, is there an internal way to regulate the power coming on,

No.

or do i just need to create a voltage divider to drive down the signal?

A resistor divider should be effective.  You may want to add a diode to clamp the divided signal to the 2.5V rail to protect against overshoots.

 

Warning:  if the 15V signal "0" level is greater than 0.3 * 15V (4.5V), then a simple resistor divider may not be reliable.  If this is the case, you could use a series zener diode or a true comparator for more reliable level shifting.  Your first step is to measure the "0" and "1" logic levels of your "15V" signal.

 

-- Bob Elkind

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Summary:
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3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
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ntropy
Adventurer
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Registered: ‎09-16-2009

You stated the first step is to measure the 0-1 levels.  Ranging on the signal, I have 13-15 and 14-15; therefore a 1volt to 2 volt differential.  Do you suggest a 1N4372A zener diode or would a LM317 be a better choice with equal resistors therefore the voltage will be equal to around 2.5v?

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sebastianro
Participant
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Registered: ‎10-22-2010

Warning:  if the 15V signal "0" level is greater than 0.3 * 15V (4.5V), then a simple resistor divider may not be reliable.

 

Sorry to be a bit off topic but how did u come up with 0.3?

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eteam00
Professor
Professor
7,660 Views
Registered: ‎07-21-2009

Sorry to be a bit off topic but how did u come up with 0.3?

This isn't off-topic in the least.  It's an excellent and pertinent question.  Two-step process:

  • Check the VCCO compatibility list of UG381 Table 1-5.
  • Cross-check with DS162 Table 9.

Options for (input only, VCCO=2.5V, VCCAUX=2.5V, no VREF) are:

IOSTD          VIL(max)   x VCCO

LVTTL          0.8        .32

LVCMOS33       0.8        .32

LVCMOS25       0.7        .28

LVCMOS18       0.38       .152

LVCMOS12       0.38       .152

I2C                       .25

SMBUS          0.8        .32

SDIO                      .125

I've listed only the VIL specs, not the VIH specs.  Of the IO standards listed above, the ones most tolerant of a voltage offset in the LOW state are:

  • LVTTL
  • LVCMOS
  • SMBUS

All of these 3 have similar VIH(min) specs:  2.0V or 2.1V.

Summary:  Downscaling the 15V signal to 2.5V, and selecting LVTTL | LVCMOS | SMBUS for the input IO std should work OK as long as the signal's "0" level is no more than 0.3x of 15V before downscaling.


A "0" level on the 15V input signal which is greater than 0.3x the maximum "1" level (presumed to be 15V) would be marginal for a simple resistor divider which scales 15V down to 2.5V.

 

This all presumes that "1" level is reliably close to 15V.  There is still room for problems if the "1" level is not consistent in this regard.

 

NOTE:  This all presumes single-ended signal.  If the "15V" signal is actually a differential pair with an ~12V common mode offset, then none of this posting is in the least bit useful.

 

-- Bob Elkind

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eteam00
Professor
Professor
7,657 Views
Registered: ‎07-21-2009

You stated the first step is to measure the 0-1 levels.  Ranging on the signal, I have 13-15 and 14-15; therefore a 1volt to 2 volt differential.

Is your "15V signal" a differential pair?  What do the numbers "13-15" and "14-15" represent?

 

Please be as concise and unambiguous as possible in your response.

 

-- Bob Elkind

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sebastianro
Participant
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Registered: ‎10-22-2010

Warning:  if the 15V signal "0" level is greater than 0.3 * 15V (4.5V), then a simple resistor divider may not be reliable.

 

Sorry to be a bit off topic but how did u come up with 0.3?

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bassman59
Historian
Historian
3,829 Views
Registered: ‎02-25-2008

 


@ntropy wrote:

You stated the first step is to measure the 0-1 levels.  Ranging on the signal, I have 13-15 and 14-15; therefore a 1volt to 2 volt differential.  Do you suggest a 1N4372A zener diode or would a LM317 be a better choice with equal resistors therefore the voltage will be equal to around 2.5v?


Use an open-collector output comparator with its threshold tied to midway between the two levels, and connect the output to the FPGA I/O pin's VCCO via the usual pullup resistor.

 

----------------------------Yes, I do this for a living.
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eteam00
Professor
Professor
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Registered: ‎07-21-2009

Sorry to be a bit off topic but how did u come up with 0.3?

Already asked, and already answered.  See message #9 in this thread. 

Did you not understand the answer?

 

-- Bob Elkind

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README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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sebastianro
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Registered: ‎10-22-2010

Ah, sorry, I didn't see the answer. Thanks for the explanations

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