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Visitor mpihllwa11
Visitor
10,282 Views
Registered: ‎11-26-2012

SP605: XPS: microblaze with axi_ethernet via sfp module problem



Dear all,

 

i currently try to generate with the XPS tool (14.7) a microblaze based system for the SP605 board, which use the sfp slot for the ethernet connection via 1000BASE-X (not the phy rj45 path).

 

I configured the xps system with an axi_ethernet (v3.01a) to use the physical interface type 1000Base-X 1Gbps, S6 Transceiver Sid B, no include of io and bufg

 

I disconected the remaining GTX_CLK and MDI signals in the assembly view an generated new connections for MGT_CLK and TX/RX

 

removed the phy based contraints from ucf and added


NET "MGT_CLK_P" LOC = "A10";
NET "MGT_CLK_N" LOC = "D11";
NET "SFP_TXP" LOC = "B8";
NET "SFP_TXN" LOC = "A8";
NET "SFP_RXP" LOC = "D9";
NET "SFP_RXN" LOC = "C9";

 

During map i got the following errors:

--------

Phase 1.1  Initial Placement Analysis
ERROR:Place:1073 - Placer was unable to create RPM[BUFDS_RPMs] for the component
   ETHERNET/ETHERNET/SOFT_PCS_PMA.S6.clkingen_ML_BUFDS of type BUFDS for the
   following reason.
   The reason for this issue:
   All of the logic associated with this structure is locked and the relative
   placement of the logic violates the structure. The problem was found between
   the relative placement of BUFDS
   ETHERNET/ETHERNET/SOFT_PCS_PMA.S6.clkingen_ML_BUFDS at site BUFDS_X1Y2 and
   IPAD MGT_CLK_N at site IPAD_X0Y6.  The following components are part of this
   structure:
      BUFDS   ETHERNET/ETHERNET/SOFT_PCS_PMA.S6.clkingen_ML_BUFDS
      IPAD   MGT_CLK_N

Phase 1.1  Initial Placement Analysis (Checksum:982b95ee) REAL time: 51 secs

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

--------

Any ideas to solve these ?

 

best regards

aw

 

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1 Reply
Explorer
Explorer
10,246 Views
Registered: ‎05-31-2015

Re: SP605: XPS: microblaze with axi_ethernet via sfp module problem

Hello,

 

      I have not worked in same conditions but still the error says that the locations used in FPGA for this particular component is already located . So please check manually in FPGA design editor the locations for this component is used by some other resources in the program that you dont  want to use these pins. Sometimes pins are assigned automatically beyond UCF constraints.

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