SP605 bufpll must have PLLIN and LOCKED pins driven by the same PLL
I am using Xilinx Platform Studio to create a Blaze based platform with a high-speed serial peripheral (in and out).
I use clock_generator_0 to provide the Bit-rate clock and the Frame-rate clock, both on PLL1.
I attach these clocks (through many layers of wrappers) to a BUFPLL instance, hooking up the bit-rate clock to PLLIN, and the frame-rate clock to GCLK. From the BUFPLL, I hook up the clk_in_buf and the serdesstrobe to my ISERDES2 and OSERDES2 instances.
I get the error message:
ERROR:LIT:560 - BUFPLL symbol "brain_0/brain_0/USER_LOGIC_I/F00/U00/bufpll_inst" (output signal=brain_0/brain_0/USER_LOGIC_I/F00/U00/clk_in_buf) must have PLLIN and LOCKED pins driven by the same PLL given that ENABLE_SYNC attribute is set to TRUE.
I suspect I have two choices:
1. Add an attribute to my two clocks, which states that they come from the same PLL (which they do), or
2. Instantiate a PLL_BASE in my peripheral. I'm suspecting this can't happen, as the Blaze may have already instantiated it. Or, perhaps Blaze only instantiated one of them, and I can pass my 200MHz clock to my peripheral, and instantiate my own PLL, generating my two clocks locally.