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sharifanali
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Registered: ‎06-18-2013

SPARTAN 6 GTP PLL

I am providing a 148.5 MHz refrence clock to a GTP transceiver. Strange thing that happens is when my line rate is 297 GHz the clocks are clean and it transmits a fine signal but when the line rate changes to 1.485 GHz clock jitter goes very high and the ransmited signal becomes jitery as well. Application is triple rate SDI, all the design guides are followed (at least I think so). What could lead to such kind of behaviour? Does anyone have any idea?

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venkata
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Registered: ‎02-16-2010

How are you changing the line rate from 2.97Gbps to 1.485Gbps? If you are using DRP to change the output divider, you should be applying GTPRESET to ensure proper initialization after updating the divider.
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sharifanali
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Registered: ‎06-18-2013

Hi,

 

yes changing the line rate is through drp. but its been taken care of within a xilinx ip core. I am using "Triple Rate SDI" IP core from logicore ip generator in ISE and it should take care of the GTPRESET automatically, Isn't that right?

 

As a matter of fact I modified the IP core in a way that it doesn't change the divider and to compensate for that I changed my ref clock externally to 74.25MHz instead of 148.5 and everything works fine. I just cant figure out why after the divider, jitter is coupled into the clock.

 

I will try a manual GTPRESET to see if that was the issue.

 

-Ali

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