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Visitor 40mpg1
Visitor
803 Views
Registered: ‎11-18-2017

School project help ultrasonic rangefinder

 Hello,

 

   I am a current student learning with the Nexys 3 board. I have a MAXSONAR: Maxbotix Ultrasonic Rangefinder  (on Xilinx shop page) that hooks up to my Nexys 3 board using the PMOD slot. The sensor spec sheet says that if the RX pin is left floating or a high signal is driven to the RX pin, then it will send range data on the TX pin. My plan is below, is it sound, does it work just the way i describe below:

 

The pmod slot only has 6 pins, but the reference manual of the nexys 3 shows 10 pins, i don't know what the extra 4 pins are, and i dont know which pin is the RX and TX hook up to ( JA1-JA10).

 

Lets assume the RX pin is M10, and TX is N9, in my implementation file all i have to do is:

 

module test (

 

output wire RX,

input reg TX

 

assign RX = 1'b1;  // drive a high signal to the RX pin on the sensor so it will start sending range data on its TX pin

 

always@(TX) begin

       // store the range data in some kind of register or memory for processing in this assign block

 

 

 

) ; end module

 

my UCF file will include:

 

NET "RX" IOSTANDARD = LVCMOS33;
NET "TX" IOSTANDARD = LVCMOS33;

 

NET "RX" LOC = M10;
NET "TX" LOC = N9;

 

 

is that basically all i have to do to start receiving data through the TX pin on the sensor? I dont have the board in hand ( its in class) so i want to word out my thoughts on how i think the sensor and the board operates, any suggestions / correction is greatly appreciated.

 

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2 Replies
Xilinx Employee
Xilinx Employee
553 Views
Registered: ‎06-30-2010

Re: School project help ultrasonic rangefinder

are you still stuck with this?
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Don’t forget to reply, kudo, and accept as solution.
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Scholar u4223374
Scholar
525 Views
Registered: ‎04-26-2015

Re: School project help ultrasonic rangefinder

Looks good, apart from the 'always @(TX)' part.

 

There are a bunch of issues with that approach, but the key one is that you don't have any sort of timing. Every time that block triggers (it'll be all the time, but never mind that for now), you don't know how long it's been since the last time it triggered - the module might have been sending a continuous stream of zeros or ones for two hours, or it might have just had a single bit at 1.

 

The solution to this is to use FPGA clock. If you do some research you'll find a bunch of UART receiver examples, but I think a much more suitable method will be to just use the PWM output. UARTs are great for PCs (where accurate timing is hard) and to some extent microcontrollers (where an easy-to-use UART library is more common than an easy-to-use PWM input one) - but FPGAs are fantastic at PWM input.

 

A more suitable block might look something like this:

 

reg [9:0] counter = 10'b0;
always @(posedge clk) begin
	if ((pwm == 1'b0) && (counter != 10'b0)) begin
		// Do something
		counter <= 0;
	end else if (pwm == 1'b1) begin
		counter <= counter + 1'b1;
	end
end

This one increments the counter (I've set it to 10-bit, but it'll depend on what your clock speed is) whenever the PWM output is high. When it goes low, the counter is cleared and at this point you have a distance measurement ready to use.