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Visitor alexis_iskr
Visitor
9,748 Views
Registered: ‎05-09-2016

Several output nets for the same signal.

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Hi,

I need to feed many DAC with an output signal from the FPGA. (33.333Mhz)

 

NET  "*"      IOSTANDARD = LVCMOS33 | SUSPEND = 3STATE;

#Input clock 66.666MHz from an oscillator
NET  "sclk"      LOC = "R9";

#The output clock in order to feed3 DAC.
NET  "clk"      SLEW = FAST | DRIVE = 8;
NET  "clk"      LOC = "A8";
NET  "clk"      LOC = "M3";
NET  "clk"      LOC = "N1";

What is the state of the art in order to feed and have several pins for the same output signal ?

Should I use buffer ? Actually, like this, I'm looking at the oscilloscope (1GSp/s) with 1Mohm input impedance, I don't see anything...

If I keep only one "clk" net (comment all other), I can see a weird signal which moves from negative to 5v and looks more a triangle signal than a square... (whereas every other output signals are 0-3.3V)

 

Please teach me, I found some IOBUF or ODDR2 but I didn't understand.

 

Thank you.

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1 Solution

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Xilinx Employee
Xilinx Employee
18,429 Views
Registered: ‎09-05-2007

Re: Several output nets for the same signal.

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As you have discovered, this is one of those situations where too much drive is a bad thing. Put a high power engine in a car and don’t be surprised if you experience wheel-spin! Therefore opting for the lowest drive strength and slew rate that gets the job done is a good approach.

 

In your current situation you have ‘unterminated transmission lines’ or ‘open circuit stubs’. There is no child sitting on the swing when you push it so of course things will be different when there is. Note that drive strength is the definition of current that the output should be able to provide to the load under steady state conditions. With no load connected you really don’t need much drive current. In contrast, your last plot showed the effect of applying a 50 Ohm load. In theory, the output would need to supply 66mA into that load for the output to rise to 3.3v.

 

The simple answer is to wait until you have connected your loads and then adjust the drive strength and slew rate. Not only will your DAC devices act as a load and termination for your lines but they could also change the length of your transmission lines (e.g. they are mounted on small boards or connected via cables) changing the natural resonant frequency of them. That said, you already know that it is best to start with the lowest settings. You also know that your lines may need to be terminated properly with some resistors. Such termination is typically reserved for clock signals since it is the actual shape of the waveform that matters (i.e. the quality and timing of the rising or falling edge). Ordinary signals that are sampled on a clock edge only need to have settled at the correct level at the time that they are sampled so the shape of their waveforms is far less important (but that’s no excuse for massive ringing and overshoot etc).

 

Did you check your PAD report to see how ISE had configured your output pins? It could be that there is no observable difference between QUIET_IO and the default SLOW slew rate given that you are currently driving completely unloaded lines.

 

It is worth saying that these things are not specific to using an FPGA. However, FPGAs have been created with the capability of driving significant loads and transmission lines at high speeds (e.g. >100MHz) and it is that capability that needs to be controlled when such performance isn’t required. Many small low powered devices such as PIC microcontrollers have very limited drive capability and this can appear to provide cleaner signals; in fact they are just much slower slew rate and lower drive strengths resulting in what could be described as over-damped outputs that are only capable of operating at a few megahertz (which is enough for what they are intended).

Ken Chapman
Principal Engineer, Xilinx UK

View solution in original post

7 Replies
Xilinx Employee
Xilinx Employee
9,733 Views
Registered: ‎09-05-2007

Re: Several output nets for the same signal.

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To feed the same signal to multiple outputs simply define multiple output ports and then assign your internal signal to all of them. Something like this…

 ...

port( clk_a : out std_logic;

      clk_b : out std_logic;

      clk_c : out std_logic;

 

 

begin 

 clk_a <= clk;

 clk_b <= clk;

 clk_c <= clk;

... 

 

Then your pin assignments and attributes can be specified for each output. Your comments suggest that you are dividing a 66MHz clock by 2 in which case assign all of your outputs within a process clocked at 66MHz and each output will be registered as well.

 

As to why you observe a triangular waveform; that suggests that you are driving out to a pin that has a significant load attached to it (i.e. more than just your scope). Get past the first issue to begin with and compare what you then observe on the 3 different pins.

Ken Chapman
Principal Engineer, Xilinx UK
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Visitor alexis_iskr
Visitor
9,663 Views
Registered: ‎05-09-2016

Re: Several output nets for the same signal.

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Thank you for your help chapman.

UCF file:

 

# sclk is the clock from the external oscillator at 66.666MHz
NET "*" IOSTANDARD = LVCMOS33 | SUSPEND = 3STATE; NET "sclk" LOC = "R9"; # They are all half of the sclk.
NET "sclkfeedLogicAnalyzer" LOC = "A8"; NET "sclkG" LOC = "M3"; NET "sclkD" LOC = "N1";

Verilog module:

 

 

assign sclkD = clk;
assign sclkG = clk;
assign sclkfeedLogicAnalyzer = clk;

# clk is half of sclk
#Fclk = 33.333MHz
#Fsclk = 66.666MHz

 

"clk" is the main clock and feeds many modules inside the FPGA (two SPI modules and some other modules) and want to feed 3 DAC.

 

sclkD, sclkG and scldfeedLA:

33_333Mhz.png

 

sclk from the oscillator:

I just assign the output to the clock input in order to see if it is a problem of the pin.

66_666MHz.png

 

A simple clock (Fclk/26), 33.333Mhz / 26 = 1.28MHz, why it oscillates a lot like this ?!

ENABLE_signal.png

 

Another signal (Chip Enable for one DAC), it's supposed to be 2 periods of the clock... :

CE_signal.png

 

You can see that the voltage is not good, signals go over 3.3V and go down to -3v.

Previous signals are captured with 1Mohm input impedance oscilloscope.

 

I tried by setting 50ohms as input for oscilloscope: (sclk signal, the same one with -2v - 5v with 1Mohm input impedance)

50ohms-oscilloscope.png

 

I am a begginer with FPGA and I am sure it is a simple problem.

 

Thank you very much for helping me.

 

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Visitor alexis_iskr
Visitor
9,659 Views
Registered: ‎05-09-2016

Re: Several output nets for the same signal.

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By using a SLEW rate and a DRIVE constraint, I could get a better signal.

The default's ones were too fast and made oscillate my signals...

I read some topics on the forum and understood SLEW and DRIVE constraints are very important for the validity.

 

Thank you again !

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Xilinx Employee
Xilinx Employee
9,650 Views
Registered: ‎09-05-2007

Re: Several output nets for the same signal.

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It sounds like you have realised that what you are observing is related to ‘transmission line theory’ and how drivers and loads really need to be matched in order to transmit signals cleanly (otherwise known as ‘signal integrity’).

 

Your third plot tells us a lot and I’m so pleased that you did this particular experiment. Ideally your waveform would be a clean square wave but what we actually see is a significant ‘ringing’ as the signal initially overshoots 3.3v on the way up or undershoots 0v on the way down. Take a closer look at that ‘ringing’ and I think I can count 4 complete oscillations within each ‘ring’ lasting for approximately 160ns. That’s one oscillation cycle per 40ns and implies a resonant frequency of about 25MHz.

 

Consider the analogy of a child sitting on swing; you give the child a push and the swing naturally swings to and fro at the frequency it naturally swings at. Without any further inputs the swing gradually settles back, but nudge it at just the right time and it will keep going and can easily be made to swing with even greater amplitude. But try giving the child a push as slightly the wrong time (e.g. a little too early) and the swing and everyone involved doesn’t have a very nice time as it all becomes messy and unstable. That’s what is happening when your 33MHz output is trying to drive the line that naturally resonates at 25MHz.

 

You might like to try one more experiment in which you generate a pulse every 40ns. You could see some serious ringing then and created the perfect example of what you should NOT be doing!

 

In simple terms, this ringing is caused by combination of inductance and capacitance of the wires (or traces on the PCB) and the load connected at the end. When the output wants to drive the line High (‘1’ or 3.3v in your case) it must provide enough current to charge any capacitance and satisfy the load. That current flows through an inductance which resists change. Initially that means it resists the increase in current but it soon builds to a maximum. Looking at your third plot we can imagine that maximum current occurring as the voltage approaches 3.3v but now the inductance resists the stopping of current. As the current continues to flow it charges the capacitance of the line and load and the voltage increases above the supply level until the current stops. At which point we have an unstable situation in which the voltage across the capacitance is higher than the supply so it starts to discharge with current flowing back towards the driver. As before, the inductance first resits the change for that current to flow and then it resists the change for it to stop.

 

To prevent ringing we need to ‘match’ the driver and load impedance with that of the transmission line. It’s not always easy to be perfect but we can at least try to help the situation. Particularly clocks are normally terminated with one or a pair of resistors. Take a look at figure 2-24 in UG380 as an example of clock distribution on a board. The driver strength and slew rate can be set in a way that deliberately limits the maximum current that flows initially thereby reducing the initial overshoot (i.e. the lower the current that flows the less it has to be stopped and the less the capacitance will over charge). Of course this means your square wave will never be perfectly square (they never are) but far better that than overshoots and strange waveforms cause by ringing.

Ken Chapman
Principal Engineer, Xilinx UK
Visitor alexis_iskr
Visitor
9,619 Views
Registered: ‎05-09-2016

Re: Several output nets for the same signal.

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Chapman,

 

Exactly, I found this term (signal integrity) in another topic and I've begun to read about this subject.
At the beginning we could imagine to get a better signal with more current and a faster slew rate but I understood it's not true at all.
It is obviously like the RLC circuit or any oscillation system. We need to get the critical damping, at least for my requirement.

If the answer is simple, could you tell me how to choose the slew rate and the drive strength ? Is it by experimenting ?
Because for now, I am just checking every signals without any load (except the board's pcb and oscilloscope), but as soon as the signals will feed the 3 DACs, the DRIVE and SLEW might not be enough anymore.
This means the SLEW and DRIVE have to be set by experimenting with the load.

Just for experimenting and since I am using a Spartan 3A, I tried to use "SLEW = QUIETIO" but ISE Design suite doesn't set it... The plot are the same than in my previous post. (high slew rate and high current)
NET  "sclkD"      LOC = "N1" | SLEW = QUIETIO | DRIVE = 2;

Thank you very much for taking time to explain me, it was and is very interesting.

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Xilinx Employee
Xilinx Employee
18,430 Views
Registered: ‎09-05-2007

Re: Several output nets for the same signal.

Jump to solution

As you have discovered, this is one of those situations where too much drive is a bad thing. Put a high power engine in a car and don’t be surprised if you experience wheel-spin! Therefore opting for the lowest drive strength and slew rate that gets the job done is a good approach.

 

In your current situation you have ‘unterminated transmission lines’ or ‘open circuit stubs’. There is no child sitting on the swing when you push it so of course things will be different when there is. Note that drive strength is the definition of current that the output should be able to provide to the load under steady state conditions. With no load connected you really don’t need much drive current. In contrast, your last plot showed the effect of applying a 50 Ohm load. In theory, the output would need to supply 66mA into that load for the output to rise to 3.3v.

 

The simple answer is to wait until you have connected your loads and then adjust the drive strength and slew rate. Not only will your DAC devices act as a load and termination for your lines but they could also change the length of your transmission lines (e.g. they are mounted on small boards or connected via cables) changing the natural resonant frequency of them. That said, you already know that it is best to start with the lowest settings. You also know that your lines may need to be terminated properly with some resistors. Such termination is typically reserved for clock signals since it is the actual shape of the waveform that matters (i.e. the quality and timing of the rising or falling edge). Ordinary signals that are sampled on a clock edge only need to have settled at the correct level at the time that they are sampled so the shape of their waveforms is far less important (but that’s no excuse for massive ringing and overshoot etc).

 

Did you check your PAD report to see how ISE had configured your output pins? It could be that there is no observable difference between QUIET_IO and the default SLOW slew rate given that you are currently driving completely unloaded lines.

 

It is worth saying that these things are not specific to using an FPGA. However, FPGAs have been created with the capability of driving significant loads and transmission lines at high speeds (e.g. >100MHz) and it is that capability that needs to be controlled when such performance isn’t required. Many small low powered devices such as PIC microcontrollers have very limited drive capability and this can appear to provide cleaner signals; in fact they are just much slower slew rate and lower drive strengths resulting in what could be described as over-damped outputs that are only capable of operating at a few megahertz (which is enough for what they are intended).

Ken Chapman
Principal Engineer, Xilinx UK

View solution in original post

Visitor alexis_iskr
Visitor
9,558 Views
Registered: ‎05-09-2016

Re: Several output nets for the same signal.

Jump to solution

I understood. I am going to do some tests with the load in order to well understand everything.

 

I didn't check, I couldn't find it in the IDE Suite but I could find the file I opened with a spreadsheet program and it was well set to QUIETIO. Then no problem.

 

Again thank you very much, everything you said was very interesting !

If I have another question, I'll post it.

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