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atamez
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Registered: ‎08-02-2012

Sharing bufpll_mcb between 2 MPMC instances

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   I am using the EDK (Version 13.2) to implement a DDR3 interface with 3 MPMC instances. I would like 2 of these instances to use a common BUFPLL_MCB.  UG388, figure 3-3 shows what I am trying to do.  In the "LogiCORE IP Multi-Port Memory Controller" (DS643) on Table 2 there is a parameter "C_MSB_USE_EXTERNAL_BUFPLL" that controls whether or not the MPMC instantiates a BUFPLL_MCB.

 

  I've used the GUI in the EDK for configuring each MPMC and clock_generator instance but do not see how to set this parameter. I tried setting the parameter in the textual netlist generated from the EDK, but the MAP report still shows 

 

Number of BUFPLL_MCBs:                         3 out of       4   75%

 

This causes failure since the other BUFPLLs are already used for other purporses.  In the EDK I have shared the clock signals between the MPMC instances connected to MCB3 and MCB4. Am I missing where to set this parameter? I've looked through documentation thoroughly and believe I'm sharing clocks between the appropriate MCBs. Maybe I'm sharing the wrong instances?

 

Thanks for your help.

 

Andres Tamez

 

 

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atamez
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Registered: ‎08-02-2012

As usual as soon as I organize thoughts and ask for help I stumble across a solution.

 

First, I added the "C_MCB_USE_EXTERNAL_PLL" manually in the MHS file created by the EDK. Then I discovered that my clock sharing was wired incorrectly after reading the following from the MPMC v6.04a guide.  Design has successfully passed Mapping and is in P&R.

 

(http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf):

 

When two MPMCs are located on the same side of the device, they must both operate on the same memory clock.
The following is an Microprocessor Hardware Specification (MHS) file example of how the two MPMCs use
cascaded clock connections when they are both located on the same side of the device:
BEGIN mpmc
PARAMETER INSTANCE = MPMC_0
...
PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_o
END
BEGIN mpmc
PARAMETER INSTANCE = MPMC_1
PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1
...
PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_o
END

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atamez
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3,479 Views
Registered: ‎08-02-2012

As usual as soon as I organize thoughts and ask for help I stumble across a solution.

 

First, I added the "C_MCB_USE_EXTERNAL_PLL" manually in the MHS file created by the EDK. Then I discovered that my clock sharing was wired incorrectly after reading the following from the MPMC v6.04a guide.  Design has successfully passed Mapping and is in P&R.

 

(http://www.xilinx.com/support/documentation/ip_documentation/mpmc/v6_04_a/mpmc.pdf):

 

When two MPMCs are located on the same side of the device, they must both operate on the same memory clock.
The following is an Microprocessor Hardware Specification (MHS) file example of how the two MPMCs use
cascaded clock connections when they are both located on the same side of the device:
BEGIN mpmc
PARAMETER INSTANCE = MPMC_0
...
PORT MPMC_Clk_Mem_2x_bufpll_o = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180_bufpll_o = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0_bufpll_o = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90_bufpll_o = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock_bufpll_o = MPMC_PLL_Lock_bufpll_o
END
BEGIN mpmc
PARAMETER INSTANCE = MPMC_1
PARAMETER C_MCB_USE_EXTERNAL_BUFPLL = 1
...
PORT MPMC_Clk_Mem_2x = MPMC_Clk_Mem_2x_bufpll_o
PORT MPMC_Clk_Mem_2x_180 = MPMC_Clk_Mem_2x_180_bufpll_o
PORT MPMC_Clk_Mem_2x_CE0 = MPMC_Clk_Mem_2x_CE0_bufpll_o
PORT MPMC_Clk_Mem_2x_CE90 = MPMC_Clk_Mem_2x_CE90_bufpll_o
PORT MPMC_PLL_Lock = MPMC_PLL_Lock_bufpll_o
END

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