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Registered: ‎08-07-2013

Slave Spartan 6 DONE flag does not go high after serial daisy chain configuration attempt

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Greetings,

I am using two Spartan 6 xc6slx4-144s in a SPI serial daisy chain configuration. The SPI PROM is a M25P40 that is programmed indirectly using JTAG, programmed with the 2 .bit files. When I program the FPGAs directly through JTAG, both DONE flags go high and the board works perfectly. However, when I try to boot without JTAG and load the FPGAs from the SPI PROM, only the master FPGA gets programmed and the slave FPGA's DONE flag does not go high. I can scope the DOUT pin from the master FPGA and see that it does load the slave FPGA with data, but it is not successful, and the DONE flag stays low. I have set the master FPGA to drive the DONE pin high when it is configured, and DONE is pulled up to +3.3V by a 330ohm resistor as suggested in UG380. The INIT_B pin toggles during configuration and ends high, and it is being pulled up by a 4.7K resistor as suggested in UG380.

 

IMPACT claims to indirectly program the SPI PROM successfully, and it will pass a verification test. I can scope the MOSI and DOUT pins on the SPI and see that data flows in and out cleanly.

 

This could be unrelated, but I've noticed an error with IMPACT (version 13.2) when I generate the PROM file. If I choose a 4M size PROM (like the M25P40), IMPACT claims it is only 512K and I have to enable bitstream compression to fit it within this supposed 512K limit. If I choose 32M, it correctly states the PROM is 4M, but then the option for M25P40 disappears from the list of possible PROMs in the boundary scan menu.

 

Below are the contents of the status registers of each FPGA post-configuration:

 

Master:

'1': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 1
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[2] RESERVED : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[8] RESERVED : 0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
'1': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 1
[4] GWE STATUS : 1
[5] GHIGH STATUS : 1
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 1
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 1
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 1
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0

 

 

Slave:

'2': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[2] RESERVED : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[8] RESERVED : 0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
'2': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 0
[4] GWE STATUS : 0
[5] GHIGH STATUS : 0
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 1
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 1
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 0
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0

 

Thanks for any and all help!

 

Cheers,

Andy

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Registered: ‎08-07-2013

Okay, this issue has been resolved.

 

In UG380, under "Guidelines and Considerations for Serial Daisy Chains", it recommends setting the DriveDone bit high for the master FPGA. I had this bit set, but I also had an external pullup on the board that would cause DONE to be set high too early and cut the configuration process short. Resetting the DriveDone bit to 0 has fixed this issue.

 

-Andy

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Registered: ‎07-23-2012
Hi,

You stated that you are configuring the Master device in Master SPI configuration mode but the status register contents suggest otherwise.

Can you please confirm it?

Also share the schematic/block diagram of the configuration interface. The .prm file would also be of help in investigating this issue.

Regards,
Krishna
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Registered: ‎08-07-2013

Krishna,

Thank you for the reply!

 

I've confirmed that the device is in master serial mode by adding CONFIG CONFIG_MODE=M_SERIAL; to the .ucf file, as well as CONFIG CONFIG_MODE=S_SERIAL; to the slave device. Here are the status register contents after an unsuccessful boot attempt:

 

Master:

'1': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[2] RESERVED : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[8] RESERVED : 0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
'1': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 0
[4] GWE STATUS : 0
[5] GHIGH STATUS : 1
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 0
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 0
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 1
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0

 

And the slave device:

 

'2': Reading bootsts register contents...
[0] VALID_0 - ERROR OR END OF STARTUP (EOS) DETECTED : 1
[1] FALLBACK_0 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[2] RESERVED : 0
[3] WTO_ERROR_0 - WATCHDOG TIME OUT ERROR : 0
[4] ID_ERROR_0 - FPGA DEVICE IDCODE ERROR : 0
[5] CRC_ERROR_0 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[6] VALID_1 - ERROR OR END OF STARTUP (EOS) DETECTED : 0
[7] FALLBACK_1 - FALLBACK RECONFIGURATION ATTEMPT DETECTED : 0
[8] RESERVED : 0
[9] WTO_ERROR_1 - WATCHDOG TIME OUT ERROR : 0
[10] ID_ERROR_1 - FPGA DEVICE IDCODE ERROR : 0
[11] CRC_ERROR_1 - CYCLIC REDUNDANCY CHECK (CRC) ERROR : 0
[12] STRIKE CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[13] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[14] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
[15] STRIKE_CNT - STRIKE COUNT FOR FALLBACK ATTEMPTS : 0
'2': Reading status register contents...
[0] CRC ERROR : 0
[1] IDCODE ERROR : 0
[2] DCM LOCK STATUS : 1
[3] GTS_CFG_B STATUS : 1
[4] GWE STATUS : 1
[5] GHIGH STATUS : 1
[6] DECRYPTION ERROR : 0
[7] DECRYPTOR ENABLE : 0
[8] HSWAPEN PIN : 1
[9] MODE PIN M[0] : 1
[10] MODE PIN M[1] : 1
[11] RESERVED : 0
[12] INIT_B PIN : 1
[13] DONE PIN : 1
[14] SUSPEND STATUS : 0
[15] FALLBACK STATUS : 0

 

This time, you'll notice that the DONE flag has gone to 1. I have left the DONE pins connected this time using a hardware switch, so it is being pulled above a logic '1' to about 1.8V but if I were to disconnect the master DONE from the slave DONE, the slave DONE will assert itself low, despite the pullup on the slave side.

 

When I scope the board, I see a clean square wave on the DOUT pin of the master into the DIN pin of the slave. Just to confirm, when I am creating the .mcs file in IMPACT, I need to assign the slave device first? Only when I assign the slave device first do I see the master FPGA attempt to program the slave FPGA upon bootup. I'll attach a picture to better illustrate what I mean. You might also see that the CCLK net simply has a serial resistor, but examining on the oscilloscope shows a very clean CCLK signal.

 

I've attached the schematic, a screenshot from IMPACT, and the .PRM file from the .mcs generation.

 

Thank you very much for the reply and your help,

 

Andy

FPGA_Config.png
IMPACT screenshot.png
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Registered: ‎08-07-2013

I'll also add that CCLK continues to run minutes after startup, so it appears to be stuck in configuration mode.

 

-Andy

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10,645 Views
Registered: ‎08-07-2013

Okay, this issue has been resolved.

 

In UG380, under "Guidelines and Considerations for Serial Daisy Chains", it recommends setting the DriveDone bit high for the master FPGA. I had this bit set, but I also had an external pullup on the board that would cause DONE to be set high too early and cut the configuration process short. Resetting the DriveDone bit to 0 has fixed this issue.

 

-Andy

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