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Visitor
Visitor
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Registered: ‎03-12-2009

Spartan 3 Starter Board External and internal Memory

Hi,

 

I am working with the Spartan 3 starter board and I am trying to use one of the internal SRAM and an external EEPROM at the same time.  This board provides external connection of the address bus and the eight less significant bits of the data buss, but I need a 16 bits data bus in the outside, so I decided to put the 8 most significant bits of the data connected to I/O ports.  When this is done, I had a problem because inside of the FPGA I has to short the most significant bits of the data path to the 8 I/O ports in a bidirectional way and I can not find a way to do this in a synthesizable way.

 

Can you help me with this?

 

How can I write a VHDL code that do this when synthesized in Xilinx? 

 

Thanks,

 

Edgar

Message Edited by edgarmarti on 03-13-2009 07:32 AM
Message Edited by edgarmarti on 03-13-2009 07:46 AM
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