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Visitor nj176
Visitor
3,113 Views
Registered: ‎08-18-2017

Spartan - 3A ADC and DAC interface

Hello!

 

I am currently working on a project to interface ADC and DAC of Spartan-3A board. I have tested the amplifier output at the amplifier chip pin with a fine probe and obtained the expected output. However, I am having some issues with the ADC interface because of which I am not able to interface the DAC of the board. 

 

I have used a logic analyzer to read the following signals:

AD_CONV = Channel 0

SPI_SCK = Channel 1

SPI_MISO (AD_OUT) = Channel 6

 

However, as can be seen from the result of the logic analyzer (image), the AD_CONV signal is not periodic. I have tried to make it periodic by using a wait statement and other ways, but all fails and the signal, along with the clock sometimes, totally disappears. 

Can anyone help me fix this issue? I have attached the image and the code.

 

Thanks in advance! 

Unbenannt.PNG
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5 Replies
Voyager
Voyager
3,107 Views
Registered: ‎06-24-2013

Re: Spartan - 3A ADC and DAC interface

Hey @nj176,

 

What's the clock frequency for the communication with the ADC (i.e. clk_div/2)?

 

Thanks,

Herbert

-------------- Yes, I do this for fun!
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Visitor nj176
Visitor
3,097 Views
Registered: ‎08-18-2017

Re: Spartan - 3A ADC and DAC interface

Hello @hpoetzl

 

From the logic analyzer, I can see that the frequency is 2MHz. However, as I have connected the input clk_div to the 50MHz crystal clock, I am kind of confused about why it is 2MHz. I had tried lowering the frequency to 1MHz and even 25KHz but that didn't really affect anything. 

 

Thanks!

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Voyager
Voyager
3,079 Views
Registered: ‎06-24-2013

Re: Spartan - 3A ADC and DAC interface

Hey @nj176,

 

... as I have connected the input clk_div to the 50MHz crystal clock ...

Yeah, that's what I expected when looking at the Saleae trace.

 

The problem here is, that your logic analyzer is running at 16MHz sample rate and you are sampling a 25Mhz signal - which simply won't work. You should use at least 50Mhz, better 100Mhz or more to sample the signals or if the analyzer cannot handle this speed, reduce the clock frequency for your design to 5Mhz instead of 50Mhz.

 

Hope this helps,

Herbert

-------------- Yes, I do this for fun!
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Visitor nj176
Visitor
3,053 Views
Registered: ‎08-18-2017

Re: Spartan - 3A ADC and DAC interface

Hey @hpoetzl!

 

Thank you for your prompt reply! :D I highly appreciate it! 

 

I lowered the clock frequency to 25kHz and the result is shown below. the first image is when the clock is continuously displayed. However, in the second image shows how the clock actually works when the clock state is applied. 

 

As you can see the AD_CONV signal is not period and does not occur after 34 cycles, as expected. 

 

Unbenannt - Without Switching on & off clock.PNG
Unbenannt - SPI_SCK.PNG
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Voyager
Voyager
3,029 Views
Registered: ‎06-24-2013

Re: Spartan - 3A ADC and DAC interface

Hey @nj176,

 

Thank you for your prompt reply! :D I highly appreciate it! 

You're welcome!

 

I lowered the clock frequency to 25kHz and the result is shown below.

With clk_div at 25kHz a clock period is 40us long so, the smallest visible feature would be 20us.

Basically every feature in the second logic analyzer capture is way shorter than 20us so there are three options:

  • Your clk_div is not at 25kHz but way higher
  • Your logic analyzer is broken or misconfigured (input voltage range for example)
  • You are measuring something else than described

And indeed, the code you attached shows a (somewhat weird) gated clock divider driving SPI_SCK but your state machine running at clk_div which is kind of modulating the signal at 50MHz. Which also matches the logic analyzer traces shown.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!