cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
5,432 Views
Registered: ‎04-29-2016

Spartan 3A - Strange Voltage Levels on CCLK

Jump to solution

I’m able to successfully load my bitsteam from SPI flash (M25P16) with the FPGA in SPI master mode (M2=0, M1=0, M0=1). But I notice strange logic levels on the configuration clock (CCLK). While it’s loading, logic low only goes down to 0.5V but logic high is fine at 3.3V. Before and after loading, CCLK is a static 1.6V and actively being driven so this can’t be due to pullup/pulldown/keeper.

 

The “Spartan-3 Generation Configuration User Guide” doesn’t mention the behavior I’m seeing. It also says CCLK becomes a user configurable pin (which I don’t use) after DONE so it should float after initialization. I double checked my board layout and nothing else drives CCLK. I even checked this on an old Digilent Spartan 3A Starter Kit eval board and it does the same thing. What is going on?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Visitor
Visitor
9,981 Views
Registered: ‎04-29-2016

Re: Spartan 3A - Strange Voltage Levels on CCLK

Jump to solution

I found the problem. The hardware layout added 100 ohm pull up AND pull down to the FPGA CCLK signal. This explains the 1.6 volts (half 3.3V). The hardware designer did this to "terminate" CCK at 50 ohms (see figure 4 in this document). Yikes! Guess where he got this idea -- the Digilent Spartan 3A eval board does the same thing! We'll have to evaluate if this is proper (logic low is questionable) but at least I now know what is causing the "Strange Voltage Levels".

View solution in original post

0 Kudos
3 Replies
Highlighted
Scholar
Scholar
5,386 Views
Registered: ‎02-27-2008

Re: Spartan 3A - Strange Voltage Levels on CCLK

Jump to solution

r,

 

Sounds like crosstalk to the pin from some other trace or pin adjacent.  To check, you could put a 1K to ground on CCLK -- if the signal is attenuated, then it is crosstalk, and of no concern.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Highlighted
Visitor
Visitor
9,982 Views
Registered: ‎04-29-2016

Re: Spartan 3A - Strange Voltage Levels on CCLK

Jump to solution

I found the problem. The hardware layout added 100 ohm pull up AND pull down to the FPGA CCLK signal. This explains the 1.6 volts (half 3.3V). The hardware designer did this to "terminate" CCK at 50 ohms (see figure 4 in this document). Yikes! Guess where he got this idea -- the Digilent Spartan 3A eval board does the same thing! We'll have to evaluate if this is proper (logic low is questionable) but at least I now know what is causing the "Strange Voltage Levels".

View solution in original post

0 Kudos
Highlighted
Scholar
Scholar
5,216 Views
Registered: ‎02-27-2008

Re: Spartan 3A - Strange Voltage Levels on CCLK

Jump to solution

r,

 

Even changing the resistors to 220, or 470 ohms each might terminate well enough.  I would look at the signal integrity with no resistors, and with 470 ohms.  It does not have to be a perfect match to work reliably.

 

The other choice is to remove both, and 'teepee' a series 100 ohm and 0.01uF chip cap to terminate AC coupled (which is fine for a clock).  While not pretty, it is an acceptable fix until a board respin (can be done such that its quality is acceptable during inspection).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos